1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define MACH_TYPE_MCX 3656 24 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 25 26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap.h> 30 31 /* 32 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 33 * and older u-boot.bin with the new U-Boot SPL. 34 */ 35 #define CONFIG_SYS_TEXT_BASE 0x80008000 36 37 /* Clock Defines */ 38 #define V_OSCK 26000000 /* Clock output from T2 */ 39 #define V_SCLK (V_OSCK >> 1) 40 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 45 #define CONFIG_INITRD_TAG 46 #define CONFIG_REVISION_TAG 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 52 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 53 /* 54 * DDR related 55 */ 56 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 57 58 /* 59 * Hardware drivers 60 */ 61 62 /* 63 * NS16550 Configuration 64 */ 65 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 66 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 3 75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 76 #define CONFIG_SERIAL3 3 /* UART3 */ 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 82 115200} 83 #define CONFIG_GENERIC_MMC 84 85 /* EHCI */ 86 #define CONFIG_OMAP3_GPIO_2 87 #define CONFIG_OMAP3_GPIO_5 88 #define CONFIG_USB_EHCI 89 #define CONFIG_USB_EHCI_OMAP 90 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 91 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 92 #define CONFIG_USB_HOST_ETHER 93 #define CONFIG_USB_ETHER_ASIX 94 #define CONFIG_USB_ETHER_MCS7830 95 96 /* commands to include */ 97 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 98 99 #define CONFIG_CMD_DATE 100 #define CONFIG_CMD_NAND /* NAND support */ 101 #define CONFIG_CMD_UBIFS 102 #define CONFIG_RBTREE 103 #define CONFIG_LZO 104 #define CONFIG_MTD_PARTITIONS 105 #define CONFIG_MTD_DEVICE 106 #define CONFIG_CMD_MTDPARTS 107 108 #define CONFIG_SYS_NO_FLASH 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 111 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 112 #define CONFIG_SYS_I2C_OMAP34XX 113 114 /* RTC */ 115 #define CONFIG_RTC_DS1337 116 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 117 118 /* 119 * Board NAND Info. 120 */ 121 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 122 /* to access nand */ 123 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 124 /* to access */ 125 /* nand at CS0 */ 126 127 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 128 /* NAND devices */ 129 #define CONFIG_JFFS2_NAND 130 /* nand device jffs2 lives on */ 131 #define CONFIG_JFFS2_DEV "nand0" 132 /* start of jffs2 partition */ 133 #define CONFIG_JFFS2_PART_OFFSET 0x680000 134 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 135 136 /* Environment information */ 137 138 #define CONFIG_BOOTFILE "uImage" 139 140 /* Setup MTD for NAND on the SOM */ 141 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 142 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 143 "1m(u-boot),256k(env1)," \ 144 "256k(env2),6m(kernel),6m(k_recovery)," \ 145 "8m(fs_recovery),-(common_data)" 146 147 #define CONFIG_HOSTNAME mcx 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 150 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 151 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 152 "addfb=setenv bootargs ${bootargs} vram=6M " \ 153 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 154 "addip_sta=setenv bootargs ${bootargs} " \ 155 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 156 "${netmask}:${hostname}:eth0:off\0" \ 157 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 158 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 159 "else run addip_sta;fi\0" \ 160 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 161 "addtty=setenv bootargs ${bootargs} " \ 162 "console=${consoledev},${baudrate}\0" \ 163 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 164 "baudrate=115200\0" \ 165 "consoledev=ttyO2\0" \ 166 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 167 "loadaddr=0x82000000\0" \ 168 "load=tftp ${loadaddr} ${u-boot}\0" \ 169 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 170 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 171 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 172 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 173 "mmcargs=root=/dev/mmcblk0p2 rw " \ 174 "rootfstype=ext3 rootwait\0" \ 175 "mmcboot=echo Booting from mmc ...; " \ 176 "run mmcargs; " \ 177 "run addip addtty addmtd addfb addeth addmisc;" \ 178 "run loaduimage; " \ 179 "bootm ${loadaddr}\0" \ 180 "net_nfs=run load_k; " \ 181 "run nfsargs; " \ 182 "run addip addtty addmtd addfb addeth addmisc;" \ 183 "bootm ${loadaddr}\0" \ 184 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 185 "nfsroot=${serverip}:${rootpath}\0" \ 186 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 187 "uboot_addr=0x80000\0" \ 188 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 189 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 190 "updatemlo=nandecc hw;nand erase 0 20000;" \ 191 "nand write ${loadaddr} 0 20000\0" \ 192 "upd=if run load;then echo Updating u-boot;if run update;" \ 193 "then echo U-Boot updated;" \ 194 "else echo Error updating u-boot !;" \ 195 "echo Board without bootloader !!;" \ 196 "fi;" \ 197 "else echo U-Boot not downloaded..exiting;fi\0" \ 198 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 199 "bootscript=echo Running bootscript from mmc ...; " \ 200 "source ${loadaddr}\0" \ 201 "nandargs=setenv bootargs ubi.mtd=7 " \ 202 "root=ubi0:rootfs rootfstype=ubifs\0" \ 203 "nandboot=echo Booting from nand ...; " \ 204 "run nandargs; " \ 205 "ubi part nand0,4;" \ 206 "ubi readvol ${loadaddr} kernel;" \ 207 "run addtty addmtd addfb addeth addmisc;" \ 208 "bootm ${loadaddr}\0" \ 209 "preboot=ubi part nand0,7;" \ 210 "ubi readvol ${loadaddr} splash;" \ 211 "bmp display ${loadaddr};" \ 212 "gpio set 55\0" \ 213 "swupdate_args=setenv bootargs root=/dev/ram " \ 214 "quiet loglevel=1 " \ 215 "consoleblank=0 ${swupdate_misc}\0" \ 216 "swupdate=echo Running Sw-Update...;" \ 217 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 218 "else mtdparts default;fi; " \ 219 "ubi part nand0,5;" \ 220 "ubi readvol 0x82000000 kernel_recovery;" \ 221 "ubi part nand0,6;" \ 222 "ubi readvol 0x84000000 fs_recovery;" \ 223 "run swupdate_args; " \ 224 "setenv bootargs ${bootargs} " \ 225 "${mtdparts} " \ 226 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 227 "omapdss.def_disp=lcd;" \ 228 "bootm 0x82000000 0x84000000\0" \ 229 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 230 "then source 82000000;else run nandboot;fi\0" 231 232 #define CONFIG_AUTO_COMPLETE 233 #define CONFIG_CMDLINE_EDITING 234 235 /* 236 * Miscellaneous configurable options 237 */ 238 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 239 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 240 /* Print Buffer Size */ 241 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 242 sizeof(CONFIG_SYS_PROMPT) + 16) 243 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 244 /* args */ 245 /* Boot Argument Buffer Size */ 246 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 247 /* memtest works on */ 248 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 249 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 250 0x01F00000) /* 31MB */ 251 252 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 253 /* address */ 254 #define CONFIG_PREBOOT 255 256 /* 257 * AM3517 has 12 GP timers, they can be driven by the system clock 258 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 259 * This rate is divided by a local divisor. 260 */ 261 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 262 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 263 264 /* 265 * Physical Memory Map 266 */ 267 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 268 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 269 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 270 271 /* 272 * FLASH and environment organization 273 */ 274 275 /* **** PISMO SUPPORT *** */ 276 #define CONFIG_NAND 277 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 278 #define CONFIG_NAND_OMAP_GPMC 279 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 280 #define CONFIG_ENV_IS_IN_NAND 281 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 282 283 /* Redundant Environment */ 284 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 285 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 286 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 287 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 288 2 * CONFIG_SYS_ENV_SECT_SIZE) 289 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 290 291 /* Flash banks JFFS2 should use */ 292 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 293 CONFIG_SYS_MAX_NAND_DEVICE) 294 #define CONFIG_SYS_JFFS2_MEM_NAND 295 /* use flash_info[2] */ 296 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 297 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 298 299 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 300 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 301 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 302 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 303 CONFIG_SYS_INIT_RAM_SIZE - \ 304 GENERATED_GBL_DATA_SIZE) 305 306 /* Defines for SPL */ 307 #define CONFIG_SPL_FRAMEWORK 308 #define CONFIG_SPL_BOARD_INIT 309 #define CONFIG_SPL_NAND_SIMPLE 310 311 #define CONFIG_SPL_NAND_BASE 312 #define CONFIG_SPL_NAND_DRIVERS 313 #define CONFIG_SPL_NAND_ECC 314 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 315 316 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 317 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 318 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 319 320 /* move malloc and bss high to prevent clashing with the main image */ 321 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 322 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 323 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 324 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 325 326 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 327 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 328 329 /* NAND boot config */ 330 #define CONFIG_SYS_NAND_PAGE_COUNT 64 331 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 332 #define CONFIG_SYS_NAND_OOBSIZE 64 333 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 334 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 335 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 336 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 337 48, 49, 50, 51, 52, 53, 54, 55,\ 338 56, 57, 58, 59, 60, 61, 62, 63} 339 #define CONFIG_SYS_NAND_ECCSIZE 256 340 #define CONFIG_SYS_NAND_ECCBYTES 3 341 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 342 #define CONFIG_SPL_NAND_SOFTECC 343 344 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 345 346 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 347 348 /* 349 * ethernet support 350 * 351 */ 352 #if defined(CONFIG_CMD_NET) 353 #define CONFIG_DRIVER_TI_EMAC 354 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 355 #define CONFIG_MII 356 #define CONFIG_BOOTP_DNS 357 #define CONFIG_BOOTP_DNS2 358 #define CONFIG_BOOTP_SEND_HOSTNAME 359 #define CONFIG_NET_RETRY_COUNT 10 360 #endif 361 362 #define CONFIG_SPLASH_SCREEN 363 #define CONFIG_VIDEO_BMP_RLE8 364 #define CONFIG_CMD_BMP 365 #define CONFIG_VIDEO_OMAP3 366 367 #endif /* __CONFIG_H */ 368