1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 4 * 5 * Based on omap3_evm_config.h 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 15 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 16 17 #include <asm/arch/cpu.h> /* get chip and board defs */ 18 #include <asm/arch/omap.h> 19 20 /* 21 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 22 * and older u-boot.bin with the new U-Boot SPL. 23 */ 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_REVISION_TAG 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 38 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 39 /* 40 * DDR related 41 */ 42 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 43 44 /* 45 * Hardware drivers 46 */ 47 48 /* 49 * NS16550 Configuration 50 */ 51 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 52 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 56 57 /* 58 * select serial console configuration 59 */ 60 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 61 #define CONFIG_SERIAL3 3 /* UART3 */ 62 63 /* allow to overwrite serial and ethaddr */ 64 #define CONFIG_ENV_OVERWRITE 65 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 66 115200} 67 68 /* EHCI */ 69 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 70 71 /* commands to include */ 72 73 #define CONFIG_SYS_I2C 74 75 /* RTC */ 76 #define CONFIG_RTC_DS1337 77 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 78 79 /* 80 * Board NAND Info. 81 */ 82 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 83 /* to access */ 84 /* nand at CS0 */ 85 86 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 87 /* NAND devices */ 88 #define CONFIG_JFFS2_NAND 89 /* nand device jffs2 lives on */ 90 #define CONFIG_JFFS2_DEV "nand0" 91 /* start of jffs2 partition */ 92 #define CONFIG_JFFS2_PART_OFFSET 0x680000 93 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 94 95 /* Environment information */ 96 97 #define CONFIG_BOOTFILE "uImage" 98 99 /* Setup MTD for NAND on the SOM */ 100 101 #define CONFIG_HOSTNAME "mcx" 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 104 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 105 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 106 "addfb=setenv bootargs ${bootargs} vram=6M " \ 107 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 108 "addip_sta=setenv bootargs ${bootargs} " \ 109 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 110 "${netmask}:${hostname}:eth0:off\0" \ 111 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 112 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 113 "else run addip_sta;fi\0" \ 114 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 115 "addtty=setenv bootargs ${bootargs} " \ 116 "console=${consoledev},${baudrate}\0" \ 117 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 118 "baudrate=115200\0" \ 119 "consoledev=ttyO2\0" \ 120 "hostname=" CONFIG_HOSTNAME "\0" \ 121 "loadaddr=0x82000000\0" \ 122 "load=tftp ${loadaddr} ${u-boot}\0" \ 123 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 124 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 125 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 126 "mlo=" CONFIG_HOSTNAME "/MLO\0" \ 127 "mmcargs=root=/dev/mmcblk0p2 rw " \ 128 "rootfstype=ext3 rootwait\0" \ 129 "mmcboot=echo Booting from mmc ...; " \ 130 "run mmcargs; " \ 131 "run addip addtty addmtd addfb addeth addmisc;" \ 132 "run loaduimage; " \ 133 "bootm ${loadaddr}\0" \ 134 "net_nfs=run load_k; " \ 135 "run nfsargs; " \ 136 "run addip addtty addmtd addfb addeth addmisc;" \ 137 "bootm ${loadaddr}\0" \ 138 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 139 "nfsroot=${serverip}:${rootpath}\0" \ 140 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ 141 "uboot_addr=0x80000\0" \ 142 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 143 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 144 "updatemlo=nandecc hw;nand erase 0 20000;" \ 145 "nand write ${loadaddr} 0 20000\0" \ 146 "upd=if run load;then echo Updating u-boot;if run update;" \ 147 "then echo U-Boot updated;" \ 148 "else echo Error updating u-boot !;" \ 149 "echo Board without bootloader !!;" \ 150 "fi;" \ 151 "else echo U-Boot not downloaded..exiting;fi\0" \ 152 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 153 "bootscript=echo Running bootscript from mmc ...; " \ 154 "source ${loadaddr}\0" \ 155 "nandargs=setenv bootargs ubi.mtd=7 " \ 156 "root=ubi0:rootfs rootfstype=ubifs\0" \ 157 "nandboot=echo Booting from nand ...; " \ 158 "run nandargs; " \ 159 "ubi part nand0,4;" \ 160 "ubi readvol ${loadaddr} kernel;" \ 161 "run addtty addmtd addfb addeth addmisc;" \ 162 "bootm ${loadaddr}\0" \ 163 "preboot=ubi part nand0,7;" \ 164 "ubi readvol ${loadaddr} splash;" \ 165 "bmp display ${loadaddr};" \ 166 "gpio set 55\0" \ 167 "swupdate_args=setenv bootargs root=/dev/ram " \ 168 "quiet loglevel=1 " \ 169 "consoleblank=0 ${swupdate_misc}\0" \ 170 "swupdate=echo Running Sw-Update...;" \ 171 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 172 "else mtdparts default;fi; " \ 173 "ubi part nand0,5;" \ 174 "ubi readvol 0x82000000 kernel_recovery;" \ 175 "ubi part nand0,6;" \ 176 "ubi readvol 0x84000000 fs_recovery;" \ 177 "run swupdate_args; " \ 178 "setenv bootargs ${bootargs} " \ 179 "${mtdparts} " \ 180 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 181 "omapdss.def_disp=lcd;" \ 182 "bootm 0x82000000 0x84000000\0" \ 183 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 184 "then source 82000000;else run nandboot;fi\0" 185 186 /* 187 * Miscellaneous configurable options 188 */ 189 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 190 /* Boot Argument Buffer Size */ 191 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 192 /* memtest works on */ 193 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 194 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 195 0x01F00000) /* 31MB */ 196 197 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 198 /* address */ 199 #define CONFIG_PREBOOT 200 201 /* 202 * AM3517 has 12 GP timers, they can be driven by the system clock 203 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 204 * This rate is divided by a local divisor. 205 */ 206 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 207 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 208 209 /* 210 * Physical Memory Map 211 */ 212 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 213 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 214 215 /* 216 * FLASH and environment organization 217 */ 218 219 /* **** PISMO SUPPORT *** */ 220 221 /* Redundant Environment */ 222 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 223 #define CONFIG_ENV_OFFSET 0x180000 224 #define CONFIG_ENV_ADDR 0x180000 225 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 226 2 * CONFIG_SYS_ENV_SECT_SIZE) 227 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 228 229 /* Flash banks JFFS2 should use */ 230 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 231 CONFIG_SYS_MAX_NAND_DEVICE) 232 #define CONFIG_SYS_JFFS2_MEM_NAND 233 /* use flash_info[2] */ 234 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 235 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 236 237 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 238 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 239 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 240 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 241 CONFIG_SYS_INIT_RAM_SIZE - \ 242 GENERATED_GBL_DATA_SIZE) 243 244 /* Defines for SPL */ 245 246 #define CONFIG_SPL_NAND_BASE 247 #define CONFIG_SPL_NAND_DRIVERS 248 #define CONFIG_SPL_NAND_ECC 249 250 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 251 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 252 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 253 254 /* move malloc and bss high to prevent clashing with the main image */ 255 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 256 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 257 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 258 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 259 260 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 261 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 262 263 /* NAND boot config */ 264 #define CONFIG_SYS_NAND_PAGE_COUNT 64 265 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 266 #define CONFIG_SYS_NAND_OOBSIZE 64 267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 268 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 269 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 270 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 271 48, 49, 50, 51, 52, 53, 54, 55,\ 272 56, 57, 58, 59, 60, 61, 62, 63} 273 #define CONFIG_SYS_NAND_ECCSIZE 256 274 #define CONFIG_SYS_NAND_ECCBYTES 3 275 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 276 #define CONFIG_SPL_NAND_SOFTECC 277 278 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 279 280 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 281 282 /* 283 * ethernet support 284 * 285 */ 286 #if defined(CONFIG_CMD_NET) 287 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 288 #define CONFIG_BOOTP_DNS2 289 #define CONFIG_BOOTP_SEND_HOSTNAME 290 #define CONFIG_NET_RETRY_COUNT 10 291 #endif 292 293 #define CONFIG_SPLASH_SCREEN 294 #define CONFIG_VIDEO_BMP_RLE8 295 #define CONFIG_VIDEO_OMAP3 296 297 #endif /* __CONFIG_H */ 298