1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP34XX /* which is a 34XX */ 17 #define CONFIG_OMAP3_MCX /* working with mcx */ 18 #define CONFIG_OMAP_GPIO 19 #define CONFIG_OMAP_COMMON 20 21 #define MACH_TYPE_MCX 3656 22 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 23 #define CONFIG_BOARD_LATE_INIT 24 25 #define CONFIG_SYS_CACHELINE_SIZE 64 26 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap3.h> 31 32 #define CONFIG_OF_LIBFDT 33 #define CONFIG_FIT 34 35 /* 36 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 37 * and older u-boot.bin with the new U-Boot SPL. 38 */ 39 #define CONFIG_SYS_TEXT_BASE 0x80008000 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_REVISION_TAG 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 63 /* 64 * DDR related 65 */ 66 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 67 68 /* 69 * Hardware drivers 70 */ 71 72 /* 73 * NS16550 Configuration 74 */ 75 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 76 77 #define CONFIG_SYS_NS16550 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 81 82 /* 83 * select serial console configuration 84 */ 85 #define CONFIG_CONS_INDEX 3 86 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 87 #define CONFIG_SERIAL3 3 /* UART3 */ 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 #define CONFIG_MMC 95 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_GENERIC_MMC 97 #define CONFIG_DOS_PARTITION 98 99 /* EHCI */ 100 #define CONFIG_USB_STORAGE 101 #define CONFIG_OMAP3_GPIO_5 102 #define CONFIG_USB_EHCI 103 #define CONFIG_USB_EHCI_OMAP 104 #define CONFIG_USB_ULPI 105 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 106 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 107 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 108 109 /* commands to include */ 110 #include <config_cmd_default.h> 111 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 113 #define CONFIG_CMD_FAT /* FAT support */ 114 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 115 116 #define CONFIG_CMD_DATE 117 #define CONFIG_CMD_I2C /* I2C serial bus support */ 118 #define CONFIG_CMD_MMC /* MMC support */ 119 #define CONFIG_CMD_FAT /* FAT support */ 120 #define CONFIG_CMD_USB 121 #define CONFIG_CMD_NAND /* NAND support */ 122 #define CONFIG_CMD_DHCP 123 #define CONFIG_CMD_PING 124 #define CONFIG_CMD_CACHE 125 #define CONFIG_CMD_UBI 126 #define CONFIG_CMD_UBIFS 127 #define CONFIG_RBTREE 128 #define CONFIG_LZO 129 #define CONFIG_MTD_PARTITIONS 130 #define CONFIG_MTD_DEVICE 131 #define CONFIG_CMD_MTDPARTS 132 #define CONFIG_CMD_GPIO 133 134 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 135 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 136 #undef CONFIG_CMD_IMI /* iminfo */ 137 #undef CONFIG_CMD_IMLS /* List all found images */ 138 139 #define CONFIG_SYS_NO_FLASH 140 #define CONFIG_HARD_I2C 141 #define CONFIG_SYS_I2C_SPEED 100000 142 #define CONFIG_SYS_I2C_SLAVE 1 143 #define CONFIG_DRIVER_OMAP34XX_I2C 144 145 /* RTC */ 146 #define CONFIG_RTC_DS1337 147 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 148 149 #define CONFIG_CMD_NET 150 #define CONFIG_CMD_MII 151 #define CONFIG_CMD_NFS 152 /* 153 * Board NAND Info. 154 */ 155 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 156 /* to access nand */ 157 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 158 /* to access */ 159 /* nand at CS0 */ 160 161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 162 /* NAND devices */ 163 #define CONFIG_JFFS2_NAND 164 /* nand device jffs2 lives on */ 165 #define CONFIG_JFFS2_DEV "nand0" 166 /* start of jffs2 partition */ 167 #define CONFIG_JFFS2_PART_OFFSET 0x680000 168 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 169 170 /* Environment information */ 171 #define CONFIG_BOOTDELAY 3 172 173 #define CONFIG_BOOTFILE "uImage" 174 175 #define xstr(s) str(s) 176 #define str(s) #s 177 178 /* Setup MTD for NAND on the SOM */ 179 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 180 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 181 "1m(u-boot),256k(env1)," \ 182 "256k(env2),6m(kernel),6m(k_recovery)," \ 183 "8m(fs_recovery),-(common_data)" 184 185 #define CONFIG_HOSTNAME mcx 186 #define CONFIG_EXTRA_ENV_SETTINGS \ 187 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 188 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 189 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 190 "addfb=setenv bootargs ${bootargs} vram=6M " \ 191 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 192 "addip_sta=setenv bootargs ${bootargs} " \ 193 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 194 "${netmask}:${hostname}:eth0:off\0" \ 195 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 196 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 197 "else run addip_sta;fi\0" \ 198 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 199 "addtty=setenv bootargs ${bootargs} " \ 200 "console=${consoledev},${baudrate}\0" \ 201 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 202 "baudrate=115200\0" \ 203 "consoledev=ttyO2\0" \ 204 "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ 205 "loadaddr=0x82000000\0" \ 206 "load=tftp ${loadaddr} ${u-boot}\0" \ 207 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 208 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 209 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 210 "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ 211 "mmcargs=root=/dev/mmcblk0p2 rw " \ 212 "rootfstype=ext3 rootwait\0" \ 213 "mmcboot=echo Booting from mmc ...; " \ 214 "run mmcargs; " \ 215 "run addip addtty addmtd addfb addeth addmisc;" \ 216 "run loaduimage; " \ 217 "bootm ${loadaddr}\0" \ 218 "net_nfs=run load_k; " \ 219 "run nfsargs; " \ 220 "run addip addtty addmtd addfb addeth addmisc;" \ 221 "bootm ${loadaddr}\0" \ 222 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 223 "nfsroot=${serverip}:${rootpath}\0" \ 224 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ 225 "uboot_addr=0x80000\0" \ 226 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 227 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 228 "updatemlo=nandecc hw;nand erase 0 20000;" \ 229 "nand write ${loadaddr} 0 20000\0" \ 230 "upd=if run load;then echo Updating u-boot;if run update;" \ 231 "then echo U-Boot updated;" \ 232 "else echo Error updating u-boot !;" \ 233 "echo Board without bootloader !!;" \ 234 "fi;" \ 235 "else echo U-Boot not downloaded..exiting;fi\0" \ 236 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 237 "bootscript=echo Running bootscript from mmc ...; " \ 238 "source ${loadaddr}\0" \ 239 "nandargs=setenv bootargs ubi.mtd=7 " \ 240 "root=ubi0:rootfs rootfstype=ubifs\0" \ 241 "nandboot=echo Booting from nand ...; " \ 242 "run nandargs; " \ 243 "ubi part nand0,4;" \ 244 "ubi readvol ${loadaddr} kernel;" \ 245 "run addtty addmtd addfb addeth addmisc;" \ 246 "bootm ${loadaddr}\0" \ 247 "preboot=ubi part nand0,7;" \ 248 "ubi readvol ${loadaddr} splash;" \ 249 "bmp display ${loadaddr};" \ 250 "gpio set 55\0" \ 251 "swupdate_args=setenv bootargs root=/dev/ram " \ 252 "quiet loglevel=1 " \ 253 "consoleblank=0 ${swupdate_misc}\0" \ 254 "swupdate=echo Running Sw-Update...;" \ 255 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 256 "else mtdparts default;fi; " \ 257 "ubi part nand0,5;" \ 258 "ubi readvol 0x82000000 kernel_recovery;" \ 259 "ubi part nand0,6;" \ 260 "ubi readvol 0x84000000 fs_recovery;" \ 261 "run swupdate_args; " \ 262 "setenv bootargs ${bootargs} " \ 263 "${mtdparts} " \ 264 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 265 "omapdss.def_disp=lcd;" \ 266 "bootm 0x82000000 0x84000000\0" 267 268 #define CONFIG_BOOTCOMMAND \ 269 "run nandboot" 270 271 #define CONFIG_AUTO_COMPLETE 272 #define CONFIG_CMDLINE_EDITING 273 274 /* 275 * Miscellaneous configurable options 276 */ 277 #define V_PROMPT "mcx # " 278 279 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 280 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 281 #define CONFIG_SYS_PROMPT V_PROMPT 282 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 283 /* Print Buffer Size */ 284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 285 sizeof(CONFIG_SYS_PROMPT) + 16) 286 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 287 /* args */ 288 /* Boot Argument Buffer Size */ 289 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 290 /* memtest works on */ 291 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 292 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 293 0x01F00000) /* 31MB */ 294 295 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 296 /* address */ 297 #define CONFIG_PREBOOT 298 299 /* 300 * AM3517 has 12 GP timers, they can be driven by the system clock 301 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 302 * This rate is divided by a local divisor. 303 */ 304 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 305 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 306 #define CONFIG_SYS_HZ 1000 307 308 /* 309 * Physical Memory Map 310 */ 311 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 312 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 313 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 314 315 /* 316 * FLASH and environment organization 317 */ 318 319 /* **** PISMO SUPPORT *** */ 320 321 /* Configure the PISMO */ 322 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 323 324 #define CONFIG_NAND_OMAP_GPMC 325 #define GPMC_NAND_ECC_LP_x16_LAYOUT 326 #define CONFIG_ENV_IS_IN_NAND 327 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 328 329 /* Redundant Environment */ 330 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 331 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 332 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 333 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 334 2 * CONFIG_SYS_ENV_SECT_SIZE) 335 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 336 337 /* Flash banks JFFS2 should use */ 338 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 339 CONFIG_SYS_MAX_NAND_DEVICE) 340 #define CONFIG_SYS_JFFS2_MEM_NAND 341 /* use flash_info[2] */ 342 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 343 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 344 345 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 346 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 347 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 348 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 349 CONFIG_SYS_INIT_RAM_SIZE - \ 350 GENERATED_GBL_DATA_SIZE) 351 352 /* Defines for SPL */ 353 #define CONFIG_SPL 354 #define CONFIG_SPL_FRAMEWORK 355 #define CONFIG_SPL_BOARD_INIT 356 #define CONFIG_SPL_NAND_SIMPLE 357 #define CONFIG_SPL_NAND_SOFTECC 358 359 #define CONFIG_SPL_LIBCOMMON_SUPPORT 360 #define CONFIG_SPL_LIBDISK_SUPPORT 361 #define CONFIG_SPL_I2C_SUPPORT 362 #define CONFIG_SPL_MMC_SUPPORT 363 #define CONFIG_SPL_FAT_SUPPORT 364 #define CONFIG_SPL_LIBGENERIC_SUPPORT 365 #define CONFIG_SPL_SERIAL_SUPPORT 366 #define CONFIG_SPL_POWER_SUPPORT 367 #define CONFIG_SPL_NAND_SUPPORT 368 #define CONFIG_SPL_NAND_BASE 369 #define CONFIG_SPL_NAND_DRIVERS 370 #define CONFIG_SPL_NAND_ECC 371 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 372 373 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 374 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 375 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 376 377 /* move malloc and bss high to prevent clashing with the main image */ 378 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 379 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 380 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 381 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 382 383 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 384 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 385 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 386 387 /* NAND boot config */ 388 #define CONFIG_SYS_NAND_PAGE_COUNT 64 389 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 390 #define CONFIG_SYS_NAND_OOBSIZE 64 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 392 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 393 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 394 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 395 48, 49, 50, 51, 52, 53, 54, 55,\ 396 56, 57, 58, 59, 60, 61, 62, 63} 397 #define CONFIG_SYS_NAND_ECCSIZE 256 398 #define CONFIG_SYS_NAND_ECCBYTES 3 399 400 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 401 402 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 403 404 /* 405 * ethernet support 406 * 407 */ 408 #if defined(CONFIG_CMD_NET) 409 #define CONFIG_DRIVER_TI_EMAC 410 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 411 #define CONFIG_MII 412 #define CONFIG_BOOTP_DNS 413 #define CONFIG_BOOTP_DNS2 414 #define CONFIG_BOOTP_SEND_HOSTNAME 415 #define CONFIG_NET_RETRY_COUNT 10 416 #endif 417 418 #define CONFIG_VIDEO 419 #define CONFIG_CFB_CONSOLE 420 #define CONFIG_VGA_AS_SINGLE_DEVICE 421 #define CONFIG_SPLASH_SCREEN 422 #define CONFIG_VIDEO_BMP_RLE8 423 #define CONFIG_CMD_BMP 424 #define CONFIG_VIDEO_OMAP3 425 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 426 427 #endif /* __CONFIG_H */ 428