1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 4 * 5 * Based on omap3_evm_config.h 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 15 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 16 17 #include <asm/arch/cpu.h> /* get chip and board defs */ 18 #include <asm/arch/omap.h> 19 20 /* 21 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 22 * and older u-boot.bin with the new U-Boot SPL. 23 */ 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MISC_INIT_R 30 31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 40 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 54 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 57 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 58 59 /* 60 * select serial console configuration 61 */ 62 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 63 #define CONFIG_SERIAL3 3 /* UART3 */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 70 /* EHCI */ 71 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 72 73 /* commands to include */ 74 75 #define CONFIG_SYS_I2C 76 77 /* RTC */ 78 #define CONFIG_RTC_DS1337 79 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 80 81 /* 82 * Board NAND Info. 83 */ 84 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 85 /* to access */ 86 /* nand at CS0 */ 87 88 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 89 /* NAND devices */ 90 #define CONFIG_JFFS2_NAND 91 /* nand device jffs2 lives on */ 92 #define CONFIG_JFFS2_DEV "nand0" 93 /* start of jffs2 partition */ 94 #define CONFIG_JFFS2_PART_OFFSET 0x680000 95 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 96 97 /* Environment information */ 98 99 #define CONFIG_BOOTFILE "uImage" 100 101 /* Setup MTD for NAND on the SOM */ 102 103 #define CONFIG_HOSTNAME "mcx" 104 #define CONFIG_EXTRA_ENV_SETTINGS \ 105 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 106 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 107 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 108 "addfb=setenv bootargs ${bootargs} vram=6M " \ 109 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 110 "addip_sta=setenv bootargs ${bootargs} " \ 111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 112 "${netmask}:${hostname}:eth0:off\0" \ 113 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 114 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 115 "else run addip_sta;fi\0" \ 116 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 117 "addtty=setenv bootargs ${bootargs} " \ 118 "console=${consoledev},${baudrate}\0" \ 119 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 120 "baudrate=115200\0" \ 121 "consoledev=ttyO2\0" \ 122 "hostname=" CONFIG_HOSTNAME "\0" \ 123 "loadaddr=0x82000000\0" \ 124 "load=tftp ${loadaddr} ${u-boot}\0" \ 125 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 126 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 127 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 128 "mlo=" CONFIG_HOSTNAME "/MLO\0" \ 129 "mmcargs=root=/dev/mmcblk0p2 rw " \ 130 "rootfstype=ext3 rootwait\0" \ 131 "mmcboot=echo Booting from mmc ...; " \ 132 "run mmcargs; " \ 133 "run addip addtty addmtd addfb addeth addmisc;" \ 134 "run loaduimage; " \ 135 "bootm ${loadaddr}\0" \ 136 "net_nfs=run load_k; " \ 137 "run nfsargs; " \ 138 "run addip addtty addmtd addfb addeth addmisc;" \ 139 "bootm ${loadaddr}\0" \ 140 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 141 "nfsroot=${serverip}:${rootpath}\0" \ 142 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ 143 "uboot_addr=0x80000\0" \ 144 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 145 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 146 "updatemlo=nandecc hw;nand erase 0 20000;" \ 147 "nand write ${loadaddr} 0 20000\0" \ 148 "upd=if run load;then echo Updating u-boot;if run update;" \ 149 "then echo U-Boot updated;" \ 150 "else echo Error updating u-boot !;" \ 151 "echo Board without bootloader !!;" \ 152 "fi;" \ 153 "else echo U-Boot not downloaded..exiting;fi\0" \ 154 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 155 "bootscript=echo Running bootscript from mmc ...; " \ 156 "source ${loadaddr}\0" \ 157 "nandargs=setenv bootargs ubi.mtd=7 " \ 158 "root=ubi0:rootfs rootfstype=ubifs\0" \ 159 "nandboot=echo Booting from nand ...; " \ 160 "run nandargs; " \ 161 "ubi part nand0,4;" \ 162 "ubi readvol ${loadaddr} kernel;" \ 163 "run addtty addmtd addfb addeth addmisc;" \ 164 "bootm ${loadaddr}\0" \ 165 "preboot=ubi part nand0,7;" \ 166 "ubi readvol ${loadaddr} splash;" \ 167 "bmp display ${loadaddr};" \ 168 "gpio set 55\0" \ 169 "swupdate_args=setenv bootargs root=/dev/ram " \ 170 "quiet loglevel=1 " \ 171 "consoleblank=0 ${swupdate_misc}\0" \ 172 "swupdate=echo Running Sw-Update...;" \ 173 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 174 "else mtdparts default;fi; " \ 175 "ubi part nand0,5;" \ 176 "ubi readvol 0x82000000 kernel_recovery;" \ 177 "ubi part nand0,6;" \ 178 "ubi readvol 0x84000000 fs_recovery;" \ 179 "run swupdate_args; " \ 180 "setenv bootargs ${bootargs} " \ 181 "${mtdparts} " \ 182 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 183 "omapdss.def_disp=lcd;" \ 184 "bootm 0x82000000 0x84000000\0" \ 185 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 186 "then source 82000000;else run nandboot;fi\0" 187 188 /* 189 * Miscellaneous configurable options 190 */ 191 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 192 /* Boot Argument Buffer Size */ 193 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 194 /* memtest works on */ 195 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 196 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 197 0x01F00000) /* 31MB */ 198 199 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 200 /* address */ 201 #define CONFIG_PREBOOT 202 203 /* 204 * AM3517 has 12 GP timers, they can be driven by the system clock 205 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 206 * This rate is divided by a local divisor. 207 */ 208 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 209 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 210 211 /* 212 * Physical Memory Map 213 */ 214 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 215 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 216 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 217 218 /* 219 * FLASH and environment organization 220 */ 221 222 /* **** PISMO SUPPORT *** */ 223 224 /* Redundant Environment */ 225 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 226 #define CONFIG_ENV_OFFSET 0x180000 227 #define CONFIG_ENV_ADDR 0x180000 228 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 229 2 * CONFIG_SYS_ENV_SECT_SIZE) 230 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 231 232 /* Flash banks JFFS2 should use */ 233 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 234 CONFIG_SYS_MAX_NAND_DEVICE) 235 #define CONFIG_SYS_JFFS2_MEM_NAND 236 /* use flash_info[2] */ 237 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 238 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 239 240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 241 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 242 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 244 CONFIG_SYS_INIT_RAM_SIZE - \ 245 GENERATED_GBL_DATA_SIZE) 246 247 /* Defines for SPL */ 248 249 #define CONFIG_SPL_NAND_BASE 250 #define CONFIG_SPL_NAND_DRIVERS 251 #define CONFIG_SPL_NAND_ECC 252 253 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 254 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 255 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 256 257 /* move malloc and bss high to prevent clashing with the main image */ 258 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 259 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 260 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 261 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 262 263 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 264 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 265 266 /* NAND boot config */ 267 #define CONFIG_SYS_NAND_PAGE_COUNT 64 268 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 269 #define CONFIG_SYS_NAND_OOBSIZE 64 270 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 271 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 272 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 273 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 274 48, 49, 50, 51, 52, 53, 54, 55,\ 275 56, 57, 58, 59, 60, 61, 62, 63} 276 #define CONFIG_SYS_NAND_ECCSIZE 256 277 #define CONFIG_SYS_NAND_ECCBYTES 3 278 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 279 #define CONFIG_SPL_NAND_SOFTECC 280 281 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 282 283 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 284 285 /* 286 * ethernet support 287 * 288 */ 289 #if defined(CONFIG_CMD_NET) 290 #define CONFIG_DRIVER_TI_EMAC 291 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 292 #define CONFIG_MII 293 #define CONFIG_BOOTP_DNS2 294 #define CONFIG_BOOTP_SEND_HOSTNAME 295 #define CONFIG_NET_RETRY_COUNT 10 296 #endif 297 298 #define CONFIG_SPLASH_SCREEN 299 #define CONFIG_VIDEO_BMP_RLE8 300 #define CONFIG_VIDEO_OMAP3 301 302 #endif /* __CONFIG_H */ 303