1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 17 18 #include <asm/arch/cpu.h> /* get chip and board defs */ 19 #include <asm/arch/omap.h> 20 21 /* 22 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 23 * and older u-boot.bin with the new U-Boot SPL. 24 */ 25 26 /* Clock Defines */ 27 #define V_OSCK 26000000 /* Clock output from T2 */ 28 #define V_SCLK (V_OSCK >> 1) 29 30 #define CONFIG_MISC_INIT_R 31 32 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 33 #define CONFIG_SETUP_MEMORY_TAGS 34 #define CONFIG_INITRD_TAG 35 #define CONFIG_REVISION_TAG 36 37 /* 38 * Size of malloc() pool 39 */ 40 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 41 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 42 /* 43 * DDR related 44 */ 45 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 46 47 /* 48 * Hardware drivers 49 */ 50 51 /* 52 * NS16550 Configuration 53 */ 54 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 55 56 #define CONFIG_SYS_NS16550_SERIAL 57 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 58 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 59 60 /* 61 * select serial console configuration 62 */ 63 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 64 #define CONFIG_SERIAL3 3 /* UART3 */ 65 66 /* allow to overwrite serial and ethaddr */ 67 #define CONFIG_ENV_OVERWRITE 68 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 69 115200} 70 71 /* EHCI */ 72 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 73 74 /* commands to include */ 75 76 #define CONFIG_MTD_PARTITIONS 77 #define CONFIG_MTD_DEVICE 78 79 #define CONFIG_SYS_I2C 80 81 /* RTC */ 82 #define CONFIG_RTC_DS1337 83 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 84 85 /* 86 * Board NAND Info. 87 */ 88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 89 /* to access nand */ 90 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 91 /* to access */ 92 /* nand at CS0 */ 93 94 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 95 /* NAND devices */ 96 #define CONFIG_JFFS2_NAND 97 /* nand device jffs2 lives on */ 98 #define CONFIG_JFFS2_DEV "nand0" 99 /* start of jffs2 partition */ 100 #define CONFIG_JFFS2_PART_OFFSET 0x680000 101 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 102 103 /* Environment information */ 104 105 #define CONFIG_BOOTFILE "uImage" 106 107 /* Setup MTD for NAND on the SOM */ 108 109 #define CONFIG_HOSTNAME mcx 110 #define CONFIG_EXTRA_ENV_SETTINGS \ 111 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 112 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 113 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 114 "addfb=setenv bootargs ${bootargs} vram=6M " \ 115 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 116 "addip_sta=setenv bootargs ${bootargs} " \ 117 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 118 "${netmask}:${hostname}:eth0:off\0" \ 119 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 120 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 121 "else run addip_sta;fi\0" \ 122 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 123 "addtty=setenv bootargs ${bootargs} " \ 124 "console=${consoledev},${baudrate}\0" \ 125 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 126 "baudrate=115200\0" \ 127 "consoledev=ttyO2\0" \ 128 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 129 "loadaddr=0x82000000\0" \ 130 "load=tftp ${loadaddr} ${u-boot}\0" \ 131 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 132 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 133 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 134 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 135 "mmcargs=root=/dev/mmcblk0p2 rw " \ 136 "rootfstype=ext3 rootwait\0" \ 137 "mmcboot=echo Booting from mmc ...; " \ 138 "run mmcargs; " \ 139 "run addip addtty addmtd addfb addeth addmisc;" \ 140 "run loaduimage; " \ 141 "bootm ${loadaddr}\0" \ 142 "net_nfs=run load_k; " \ 143 "run nfsargs; " \ 144 "run addip addtty addmtd addfb addeth addmisc;" \ 145 "bootm ${loadaddr}\0" \ 146 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 147 "nfsroot=${serverip}:${rootpath}\0" \ 148 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 149 "uboot_addr=0x80000\0" \ 150 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 151 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 152 "updatemlo=nandecc hw;nand erase 0 20000;" \ 153 "nand write ${loadaddr} 0 20000\0" \ 154 "upd=if run load;then echo Updating u-boot;if run update;" \ 155 "then echo U-Boot updated;" \ 156 "else echo Error updating u-boot !;" \ 157 "echo Board without bootloader !!;" \ 158 "fi;" \ 159 "else echo U-Boot not downloaded..exiting;fi\0" \ 160 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 161 "bootscript=echo Running bootscript from mmc ...; " \ 162 "source ${loadaddr}\0" \ 163 "nandargs=setenv bootargs ubi.mtd=7 " \ 164 "root=ubi0:rootfs rootfstype=ubifs\0" \ 165 "nandboot=echo Booting from nand ...; " \ 166 "run nandargs; " \ 167 "ubi part nand0,4;" \ 168 "ubi readvol ${loadaddr} kernel;" \ 169 "run addtty addmtd addfb addeth addmisc;" \ 170 "bootm ${loadaddr}\0" \ 171 "preboot=ubi part nand0,7;" \ 172 "ubi readvol ${loadaddr} splash;" \ 173 "bmp display ${loadaddr};" \ 174 "gpio set 55\0" \ 175 "swupdate_args=setenv bootargs root=/dev/ram " \ 176 "quiet loglevel=1 " \ 177 "consoleblank=0 ${swupdate_misc}\0" \ 178 "swupdate=echo Running Sw-Update...;" \ 179 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 180 "else mtdparts default;fi; " \ 181 "ubi part nand0,5;" \ 182 "ubi readvol 0x82000000 kernel_recovery;" \ 183 "ubi part nand0,6;" \ 184 "ubi readvol 0x84000000 fs_recovery;" \ 185 "run swupdate_args; " \ 186 "setenv bootargs ${bootargs} " \ 187 "${mtdparts} " \ 188 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 189 "omapdss.def_disp=lcd;" \ 190 "bootm 0x82000000 0x84000000\0" \ 191 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 192 "then source 82000000;else run nandboot;fi\0" 193 194 /* 195 * Miscellaneous configurable options 196 */ 197 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 198 /* Boot Argument Buffer Size */ 199 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 200 /* memtest works on */ 201 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 202 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 203 0x01F00000) /* 31MB */ 204 205 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 206 /* address */ 207 #define CONFIG_PREBOOT 208 209 /* 210 * AM3517 has 12 GP timers, they can be driven by the system clock 211 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 212 * This rate is divided by a local divisor. 213 */ 214 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 215 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 216 217 /* 218 * Physical Memory Map 219 */ 220 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 221 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 222 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 223 224 /* 225 * FLASH and environment organization 226 */ 227 228 /* **** PISMO SUPPORT *** */ 229 230 /* Redundant Environment */ 231 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 232 #define CONFIG_ENV_OFFSET 0x180000 233 #define CONFIG_ENV_ADDR 0x180000 234 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 235 2 * CONFIG_SYS_ENV_SECT_SIZE) 236 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 237 238 /* Flash banks JFFS2 should use */ 239 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 240 CONFIG_SYS_MAX_NAND_DEVICE) 241 #define CONFIG_SYS_JFFS2_MEM_NAND 242 /* use flash_info[2] */ 243 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 244 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 245 246 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 247 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 248 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 250 CONFIG_SYS_INIT_RAM_SIZE - \ 251 GENERATED_GBL_DATA_SIZE) 252 253 /* Defines for SPL */ 254 255 #define CONFIG_SPL_NAND_BASE 256 #define CONFIG_SPL_NAND_DRIVERS 257 #define CONFIG_SPL_NAND_ECC 258 259 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 260 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 261 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 262 263 /* move malloc and bss high to prevent clashing with the main image */ 264 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 265 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 266 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 267 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 268 269 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 270 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 271 272 /* NAND boot config */ 273 #define CONFIG_SYS_NAND_PAGE_COUNT 64 274 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 275 #define CONFIG_SYS_NAND_OOBSIZE 64 276 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 277 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 278 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 279 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 280 48, 49, 50, 51, 52, 53, 54, 55,\ 281 56, 57, 58, 59, 60, 61, 62, 63} 282 #define CONFIG_SYS_NAND_ECCSIZE 256 283 #define CONFIG_SYS_NAND_ECCBYTES 3 284 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 285 #define CONFIG_SPL_NAND_SOFTECC 286 287 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 288 289 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 290 291 /* 292 * ethernet support 293 * 294 */ 295 #if defined(CONFIG_CMD_NET) 296 #define CONFIG_DRIVER_TI_EMAC 297 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 298 #define CONFIG_MII 299 #define CONFIG_BOOTP_DNS2 300 #define CONFIG_BOOTP_SEND_HOSTNAME 301 #define CONFIG_NET_RETRY_COUNT 10 302 #endif 303 304 #define CONFIG_SPLASH_SCREEN 305 #define CONFIG_VIDEO_BMP_RLE8 306 #define CONFIG_VIDEO_OMAP3 307 308 #endif /* __CONFIG_H */ 309