1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 17 18 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* 24 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 25 * and older u-boot.bin with the new U-Boot SPL. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x80008000 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_INITRD_TAG 38 #define CONFIG_REVISION_TAG 39 40 /* 41 * Size of malloc() pool 42 */ 43 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 44 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 45 /* 46 * DDR related 47 */ 48 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 49 50 /* 51 * Hardware drivers 52 */ 53 54 /* 55 * NS16550 Configuration 56 */ 57 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 58 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 61 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 62 63 /* 64 * select serial console configuration 65 */ 66 #define CONFIG_CONS_INDEX 3 67 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 68 #define CONFIG_SERIAL3 3 /* UART3 */ 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 73 115200} 74 75 /* EHCI */ 76 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 77 #define CONFIG_USB_HOST_ETHER 78 #define CONFIG_USB_ETHER_ASIX 79 #define CONFIG_USB_ETHER_MCS7830 80 81 /* commands to include */ 82 83 #define CONFIG_MTD_PARTITIONS 84 #define CONFIG_MTD_DEVICE 85 86 #define CONFIG_SYS_I2C 87 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 88 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 89 #define CONFIG_SYS_I2C_OMAP34XX 90 91 /* RTC */ 92 #define CONFIG_RTC_DS1337 93 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 94 95 /* 96 * Board NAND Info. 97 */ 98 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 99 /* to access nand */ 100 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 101 /* to access */ 102 /* nand at CS0 */ 103 104 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 105 /* NAND devices */ 106 #define CONFIG_JFFS2_NAND 107 /* nand device jffs2 lives on */ 108 #define CONFIG_JFFS2_DEV "nand0" 109 /* start of jffs2 partition */ 110 #define CONFIG_JFFS2_PART_OFFSET 0x680000 111 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 112 113 /* Environment information */ 114 115 #define CONFIG_BOOTFILE "uImage" 116 117 /* Setup MTD for NAND on the SOM */ 118 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 119 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 120 "1m(u-boot),256k(env1)," \ 121 "256k(env2),6m(kernel),6m(k_recovery)," \ 122 "8m(fs_recovery),-(common_data)" 123 124 #define CONFIG_HOSTNAME mcx 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 127 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 128 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 129 "addfb=setenv bootargs ${bootargs} vram=6M " \ 130 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 131 "addip_sta=setenv bootargs ${bootargs} " \ 132 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 133 "${netmask}:${hostname}:eth0:off\0" \ 134 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 135 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 136 "else run addip_sta;fi\0" \ 137 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 138 "addtty=setenv bootargs ${bootargs} " \ 139 "console=${consoledev},${baudrate}\0" \ 140 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 141 "baudrate=115200\0" \ 142 "consoledev=ttyO2\0" \ 143 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 144 "loadaddr=0x82000000\0" \ 145 "load=tftp ${loadaddr} ${u-boot}\0" \ 146 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 147 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 148 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 149 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 150 "mmcargs=root=/dev/mmcblk0p2 rw " \ 151 "rootfstype=ext3 rootwait\0" \ 152 "mmcboot=echo Booting from mmc ...; " \ 153 "run mmcargs; " \ 154 "run addip addtty addmtd addfb addeth addmisc;" \ 155 "run loaduimage; " \ 156 "bootm ${loadaddr}\0" \ 157 "net_nfs=run load_k; " \ 158 "run nfsargs; " \ 159 "run addip addtty addmtd addfb addeth addmisc;" \ 160 "bootm ${loadaddr}\0" \ 161 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 162 "nfsroot=${serverip}:${rootpath}\0" \ 163 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 164 "uboot_addr=0x80000\0" \ 165 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 166 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 167 "updatemlo=nandecc hw;nand erase 0 20000;" \ 168 "nand write ${loadaddr} 0 20000\0" \ 169 "upd=if run load;then echo Updating u-boot;if run update;" \ 170 "then echo U-Boot updated;" \ 171 "else echo Error updating u-boot !;" \ 172 "echo Board without bootloader !!;" \ 173 "fi;" \ 174 "else echo U-Boot not downloaded..exiting;fi\0" \ 175 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 176 "bootscript=echo Running bootscript from mmc ...; " \ 177 "source ${loadaddr}\0" \ 178 "nandargs=setenv bootargs ubi.mtd=7 " \ 179 "root=ubi0:rootfs rootfstype=ubifs\0" \ 180 "nandboot=echo Booting from nand ...; " \ 181 "run nandargs; " \ 182 "ubi part nand0,4;" \ 183 "ubi readvol ${loadaddr} kernel;" \ 184 "run addtty addmtd addfb addeth addmisc;" \ 185 "bootm ${loadaddr}\0" \ 186 "preboot=ubi part nand0,7;" \ 187 "ubi readvol ${loadaddr} splash;" \ 188 "bmp display ${loadaddr};" \ 189 "gpio set 55\0" \ 190 "swupdate_args=setenv bootargs root=/dev/ram " \ 191 "quiet loglevel=1 " \ 192 "consoleblank=0 ${swupdate_misc}\0" \ 193 "swupdate=echo Running Sw-Update...;" \ 194 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 195 "else mtdparts default;fi; " \ 196 "ubi part nand0,5;" \ 197 "ubi readvol 0x82000000 kernel_recovery;" \ 198 "ubi part nand0,6;" \ 199 "ubi readvol 0x84000000 fs_recovery;" \ 200 "run swupdate_args; " \ 201 "setenv bootargs ${bootargs} " \ 202 "${mtdparts} " \ 203 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 204 "omapdss.def_disp=lcd;" \ 205 "bootm 0x82000000 0x84000000\0" \ 206 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 207 "then source 82000000;else run nandboot;fi\0" 208 209 #define CONFIG_AUTO_COMPLETE 210 #define CONFIG_CMDLINE_EDITING 211 212 /* 213 * Miscellaneous configurable options 214 */ 215 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 216 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 217 /* Print Buffer Size */ 218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 219 sizeof(CONFIG_SYS_PROMPT) + 16) 220 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 221 /* args */ 222 /* Boot Argument Buffer Size */ 223 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 224 /* memtest works on */ 225 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 226 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 227 0x01F00000) /* 31MB */ 228 229 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 230 /* address */ 231 #define CONFIG_PREBOOT 232 233 /* 234 * AM3517 has 12 GP timers, they can be driven by the system clock 235 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 236 * This rate is divided by a local divisor. 237 */ 238 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 239 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 240 241 /* 242 * Physical Memory Map 243 */ 244 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 245 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 246 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 247 248 /* 249 * FLASH and environment organization 250 */ 251 252 /* **** PISMO SUPPORT *** */ 253 #define CONFIG_NAND 254 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 255 #define CONFIG_NAND_OMAP_GPMC 256 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 257 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 258 259 /* Redundant Environment */ 260 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 261 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 262 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 263 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 264 2 * CONFIG_SYS_ENV_SECT_SIZE) 265 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 266 267 /* Flash banks JFFS2 should use */ 268 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 269 CONFIG_SYS_MAX_NAND_DEVICE) 270 #define CONFIG_SYS_JFFS2_MEM_NAND 271 /* use flash_info[2] */ 272 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 273 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 274 275 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 276 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 277 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 279 CONFIG_SYS_INIT_RAM_SIZE - \ 280 GENERATED_GBL_DATA_SIZE) 281 282 /* Defines for SPL */ 283 #define CONFIG_SPL_FRAMEWORK 284 #define CONFIG_SPL_NAND_SIMPLE 285 286 #define CONFIG_SPL_NAND_BASE 287 #define CONFIG_SPL_NAND_DRIVERS 288 #define CONFIG_SPL_NAND_ECC 289 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 290 291 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 292 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 293 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 294 295 /* move malloc and bss high to prevent clashing with the main image */ 296 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 297 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 298 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 299 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 300 301 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 302 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 303 304 /* NAND boot config */ 305 #define CONFIG_SYS_NAND_PAGE_COUNT 64 306 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 307 #define CONFIG_SYS_NAND_OOBSIZE 64 308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 309 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 310 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 311 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 312 48, 49, 50, 51, 52, 53, 54, 55,\ 313 56, 57, 58, 59, 60, 61, 62, 63} 314 #define CONFIG_SYS_NAND_ECCSIZE 256 315 #define CONFIG_SYS_NAND_ECCBYTES 3 316 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 317 #define CONFIG_SPL_NAND_SOFTECC 318 319 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 320 321 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 322 323 /* 324 * ethernet support 325 * 326 */ 327 #if defined(CONFIG_CMD_NET) 328 #define CONFIG_DRIVER_TI_EMAC 329 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 330 #define CONFIG_MII 331 #define CONFIG_BOOTP_DNS 332 #define CONFIG_BOOTP_DNS2 333 #define CONFIG_BOOTP_SEND_HOSTNAME 334 #define CONFIG_NET_RETRY_COUNT 10 335 #endif 336 337 #define CONFIG_SPLASH_SCREEN 338 #define CONFIG_VIDEO_BMP_RLE8 339 #define CONFIG_VIDEO_OMAP3 340 341 #endif /* __CONFIG_H */ 342