1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define MACH_TYPE_MCX 3656 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 26 #define CONFIG_BOARD_LATE_INIT 27 28 29 #define CONFIG_SYS_CACHELINE_SIZE 64 30 31 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap.h> 35 36 /* 37 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 38 * and older u-boot.bin with the new U-Boot SPL. 39 */ 40 #define CONFIG_SYS_TEXT_BASE 0x80008000 41 42 /* 43 * Display CPU and Board information 44 */ 45 #define CONFIG_DISPLAY_CPUINFO 46 #define CONFIG_DISPLAY_BOARDINFO 47 48 /* Clock Defines */ 49 #define V_OSCK 26000000 /* Clock output from T2 */ 50 #define V_SCLK (V_OSCK >> 1) 51 52 #define CONFIG_MISC_INIT_R 53 54 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 55 #define CONFIG_SETUP_MEMORY_TAGS 56 #define CONFIG_INITRD_TAG 57 #define CONFIG_REVISION_TAG 58 59 /* 60 * Size of malloc() pool 61 */ 62 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 63 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 64 /* 65 * DDR related 66 */ 67 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 68 69 /* 70 * Hardware drivers 71 */ 72 73 /* 74 * NS16550 Configuration 75 */ 76 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 77 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 81 82 /* 83 * select serial console configuration 84 */ 85 #define CONFIG_CONS_INDEX 3 86 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 87 #define CONFIG_SERIAL3 3 /* UART3 */ 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 #define CONFIG_MMC 95 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_GENERIC_MMC 97 #define CONFIG_DOS_PARTITION 98 99 /* EHCI */ 100 #define CONFIG_USB_STORAGE 101 #define CONFIG_OMAP3_GPIO_2 102 #define CONFIG_OMAP3_GPIO_5 103 #define CONFIG_USB_EHCI 104 #define CONFIG_USB_EHCI_OMAP 105 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 106 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 107 #define CONFIG_USB_HOST_ETHER 108 #define CONFIG_USB_ETHER_ASIX 109 #define CONFIG_USB_ETHER_MCS7830 110 111 /* commands to include */ 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 113 #define CONFIG_CMD_FAT /* FAT support */ 114 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 115 116 #define CONFIG_CMD_DATE 117 #define CONFIG_CMD_I2C /* I2C serial bus support */ 118 #define CONFIG_CMD_MMC /* MMC support */ 119 #define CONFIG_CMD_FAT /* FAT support */ 120 #define CONFIG_CMD_USB 121 #define CONFIG_CMD_NAND /* NAND support */ 122 #define CONFIG_CMD_DHCP 123 #define CONFIG_CMD_PING 124 #define CONFIG_CMD_CACHE 125 #define CONFIG_CMD_UBI 126 #define CONFIG_CMD_UBIFS 127 #define CONFIG_RBTREE 128 #define CONFIG_LZO 129 #define CONFIG_MTD_PARTITIONS 130 #define CONFIG_MTD_DEVICE 131 #define CONFIG_CMD_MTDPARTS 132 133 #define CONFIG_SYS_NO_FLASH 134 #define CONFIG_SYS_I2C 135 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 136 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 137 #define CONFIG_SYS_I2C_OMAP34XX 138 139 /* RTC */ 140 #define CONFIG_RTC_DS1337 141 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 142 143 #define CONFIG_CMD_MII 144 /* 145 * Board NAND Info. 146 */ 147 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 148 /* to access nand */ 149 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 150 /* to access */ 151 /* nand at CS0 */ 152 153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 154 /* NAND devices */ 155 #define CONFIG_JFFS2_NAND 156 /* nand device jffs2 lives on */ 157 #define CONFIG_JFFS2_DEV "nand0" 158 /* start of jffs2 partition */ 159 #define CONFIG_JFFS2_PART_OFFSET 0x680000 160 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 161 162 /* Environment information */ 163 #define CONFIG_BOOTDELAY 3 164 165 #define CONFIG_BOOTFILE "uImage" 166 167 /* Setup MTD for NAND on the SOM */ 168 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 169 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 170 "1m(u-boot),256k(env1)," \ 171 "256k(env2),6m(kernel),6m(k_recovery)," \ 172 "8m(fs_recovery),-(common_data)" 173 174 #define CONFIG_HOSTNAME mcx 175 #define CONFIG_EXTRA_ENV_SETTINGS \ 176 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 177 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 178 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 179 "addfb=setenv bootargs ${bootargs} vram=6M " \ 180 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 181 "addip_sta=setenv bootargs ${bootargs} " \ 182 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 183 "${netmask}:${hostname}:eth0:off\0" \ 184 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 185 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 186 "else run addip_sta;fi\0" \ 187 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 188 "addtty=setenv bootargs ${bootargs} " \ 189 "console=${consoledev},${baudrate}\0" \ 190 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 191 "baudrate=115200\0" \ 192 "consoledev=ttyO2\0" \ 193 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 194 "loadaddr=0x82000000\0" \ 195 "load=tftp ${loadaddr} ${u-boot}\0" \ 196 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 197 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 198 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 199 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 200 "mmcargs=root=/dev/mmcblk0p2 rw " \ 201 "rootfstype=ext3 rootwait\0" \ 202 "mmcboot=echo Booting from mmc ...; " \ 203 "run mmcargs; " \ 204 "run addip addtty addmtd addfb addeth addmisc;" \ 205 "run loaduimage; " \ 206 "bootm ${loadaddr}\0" \ 207 "net_nfs=run load_k; " \ 208 "run nfsargs; " \ 209 "run addip addtty addmtd addfb addeth addmisc;" \ 210 "bootm ${loadaddr}\0" \ 211 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 212 "nfsroot=${serverip}:${rootpath}\0" \ 213 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 214 "uboot_addr=0x80000\0" \ 215 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 216 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 217 "updatemlo=nandecc hw;nand erase 0 20000;" \ 218 "nand write ${loadaddr} 0 20000\0" \ 219 "upd=if run load;then echo Updating u-boot;if run update;" \ 220 "then echo U-Boot updated;" \ 221 "else echo Error updating u-boot !;" \ 222 "echo Board without bootloader !!;" \ 223 "fi;" \ 224 "else echo U-Boot not downloaded..exiting;fi\0" \ 225 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 226 "bootscript=echo Running bootscript from mmc ...; " \ 227 "source ${loadaddr}\0" \ 228 "nandargs=setenv bootargs ubi.mtd=7 " \ 229 "root=ubi0:rootfs rootfstype=ubifs\0" \ 230 "nandboot=echo Booting from nand ...; " \ 231 "run nandargs; " \ 232 "ubi part nand0,4;" \ 233 "ubi readvol ${loadaddr} kernel;" \ 234 "run addtty addmtd addfb addeth addmisc;" \ 235 "bootm ${loadaddr}\0" \ 236 "preboot=ubi part nand0,7;" \ 237 "ubi readvol ${loadaddr} splash;" \ 238 "bmp display ${loadaddr};" \ 239 "gpio set 55\0" \ 240 "swupdate_args=setenv bootargs root=/dev/ram " \ 241 "quiet loglevel=1 " \ 242 "consoleblank=0 ${swupdate_misc}\0" \ 243 "swupdate=echo Running Sw-Update...;" \ 244 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 245 "else mtdparts default;fi; " \ 246 "ubi part nand0,5;" \ 247 "ubi readvol 0x82000000 kernel_recovery;" \ 248 "ubi part nand0,6;" \ 249 "ubi readvol 0x84000000 fs_recovery;" \ 250 "run swupdate_args; " \ 251 "setenv bootargs ${bootargs} " \ 252 "${mtdparts} " \ 253 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 254 "omapdss.def_disp=lcd;" \ 255 "bootm 0x82000000 0x84000000\0" \ 256 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 257 "then source 82000000;else run nandboot;fi\0" 258 259 #define CONFIG_AUTO_COMPLETE 260 #define CONFIG_CMDLINE_EDITING 261 262 /* 263 * Miscellaneous configurable options 264 */ 265 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 266 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 267 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 268 /* Print Buffer Size */ 269 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 270 sizeof(CONFIG_SYS_PROMPT) + 16) 271 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 272 /* args */ 273 /* Boot Argument Buffer Size */ 274 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 275 /* memtest works on */ 276 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 277 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 278 0x01F00000) /* 31MB */ 279 280 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 281 /* address */ 282 #define CONFIG_PREBOOT 283 284 /* 285 * AM3517 has 12 GP timers, they can be driven by the system clock 286 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 287 * This rate is divided by a local divisor. 288 */ 289 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 290 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 291 292 /* 293 * Physical Memory Map 294 */ 295 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 296 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 297 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 298 299 /* 300 * FLASH and environment organization 301 */ 302 303 /* **** PISMO SUPPORT *** */ 304 #define CONFIG_NAND 305 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 306 #define CONFIG_NAND_OMAP_GPMC 307 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 308 #define CONFIG_ENV_IS_IN_NAND 309 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 310 311 /* Redundant Environment */ 312 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 313 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 314 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 315 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 316 2 * CONFIG_SYS_ENV_SECT_SIZE) 317 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 318 319 /* Flash banks JFFS2 should use */ 320 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 321 CONFIG_SYS_MAX_NAND_DEVICE) 322 #define CONFIG_SYS_JFFS2_MEM_NAND 323 /* use flash_info[2] */ 324 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 325 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 326 327 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 328 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 329 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 330 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 331 CONFIG_SYS_INIT_RAM_SIZE - \ 332 GENERATED_GBL_DATA_SIZE) 333 334 /* Defines for SPL */ 335 #define CONFIG_SPL_FRAMEWORK 336 #define CONFIG_SPL_BOARD_INIT 337 #define CONFIG_SPL_NAND_SIMPLE 338 339 #define CONFIG_SPL_LIBCOMMON_SUPPORT 340 #define CONFIG_SPL_LIBDISK_SUPPORT 341 #define CONFIG_SPL_I2C_SUPPORT 342 #define CONFIG_SPL_MMC_SUPPORT 343 #define CONFIG_SPL_FAT_SUPPORT 344 #define CONFIG_SPL_LIBGENERIC_SUPPORT 345 #define CONFIG_SPL_SERIAL_SUPPORT 346 #define CONFIG_SPL_POWER_SUPPORT 347 #define CONFIG_SPL_NAND_SUPPORT 348 #define CONFIG_SPL_NAND_BASE 349 #define CONFIG_SPL_NAND_DRIVERS 350 #define CONFIG_SPL_NAND_ECC 351 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 352 353 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 354 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 355 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 356 357 /* move malloc and bss high to prevent clashing with the main image */ 358 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 359 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 360 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 361 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 362 363 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 364 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 365 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 366 367 /* NAND boot config */ 368 #define CONFIG_SYS_NAND_PAGE_COUNT 64 369 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 370 #define CONFIG_SYS_NAND_OOBSIZE 64 371 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 372 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 373 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 374 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 375 48, 49, 50, 51, 52, 53, 54, 55,\ 376 56, 57, 58, 59, 60, 61, 62, 63} 377 #define CONFIG_SYS_NAND_ECCSIZE 256 378 #define CONFIG_SYS_NAND_ECCBYTES 3 379 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 380 #define CONFIG_SPL_NAND_SOFTECC 381 382 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 383 384 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 385 386 /* 387 * ethernet support 388 * 389 */ 390 #if defined(CONFIG_CMD_NET) 391 #define CONFIG_DRIVER_TI_EMAC 392 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 393 #define CONFIG_MII 394 #define CONFIG_BOOTP_DNS 395 #define CONFIG_BOOTP_DNS2 396 #define CONFIG_BOOTP_SEND_HOSTNAME 397 #define CONFIG_NET_RETRY_COUNT 10 398 #endif 399 400 #define CONFIG_VIDEO 401 #define CONFIG_CFB_CONSOLE 402 #define CONFIG_VGA_AS_SINGLE_DEVICE 403 #define CONFIG_SPLASH_SCREEN 404 #define CONFIG_VIDEO_BMP_RLE8 405 #define CONFIG_CMD_BMP 406 #define CONFIG_VIDEO_OMAP3 407 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 408 409 #endif /* __CONFIG_H */ 410