xref: /openbmc/u-boot/include/configs/mcx.h (revision 568b471e)
1 /*
2  * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3  *
4  * Based on omap3_evm_config.h
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_OMAP			/* in a TI OMAP core */
16 #define CONFIG_OMAP3_MCX		/* working with mcx */
17 #define CONFIG_OMAP_GPIO
18 /* Common ARM Erratas */
19 #define CONFIG_ARM_ERRATA_454179
20 #define CONFIG_ARM_ERRATA_430973
21 #define CONFIG_ARM_ERRATA_621766
22 
23 #define MACH_TYPE_MCX			3656
24 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
25 #define CONFIG_BOARD_LATE_INIT
26 
27 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
28 
29 #include <asm/arch/cpu.h>		/* get chip and board defs */
30 #include <asm/arch/omap.h>
31 
32 /*
33  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
34  * and older u-boot.bin with the new U-Boot SPL.
35  */
36 #define CONFIG_SYS_TEXT_BASE		0x80008000
37 
38 /* Clock Defines */
39 #define V_OSCK			26000000	/* Clock output from T2 */
40 #define V_SCLK			(V_OSCK >> 1)
41 
42 #define CONFIG_MISC_INIT_R
43 
44 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS
46 #define CONFIG_INITRD_TAG
47 #define CONFIG_REVISION_TAG
48 
49 /*
50  * Size of malloc() pool
51  */
52 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
53 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
54 /*
55  * DDR related
56  */
57 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
58 
59 /*
60  * Hardware drivers
61  */
62 
63 /*
64  * NS16550 Configuration
65  */
66 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
67 
68 #define CONFIG_SYS_NS16550_SERIAL
69 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
70 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
71 
72 /*
73  * select serial console configuration
74  */
75 #define CONFIG_CONS_INDEX		3
76 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
77 #define CONFIG_SERIAL3			3	/* UART3 */
78 
79 /* allow to overwrite serial and ethaddr */
80 #define CONFIG_ENV_OVERWRITE
81 #define CONFIG_BAUDRATE			115200
82 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
83 					115200}
84 #define CONFIG_GENERIC_MMC
85 #define CONFIG_DOS_PARTITION
86 
87 /* EHCI */
88 #define CONFIG_OMAP3_GPIO_2
89 #define CONFIG_OMAP3_GPIO_5
90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_OMAP
92 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
93 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
94 #define	CONFIG_USB_HOST_ETHER
95 #define	CONFIG_USB_ETHER_ASIX
96 #define CONFIG_USB_ETHER_MCS7830
97 
98 /* commands to include */
99 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
100 
101 #define CONFIG_CMD_DATE
102 #define CONFIG_CMD_NAND		/* NAND support			*/
103 #define CONFIG_CMD_UBIFS
104 #define CONFIG_RBTREE
105 #define CONFIG_LZO
106 #define CONFIG_MTD_PARTITIONS
107 #define CONFIG_MTD_DEVICE
108 #define CONFIG_CMD_MTDPARTS
109 
110 #define CONFIG_SYS_NO_FLASH
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
113 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
114 #define CONFIG_SYS_I2C_OMAP34XX
115 
116 /* RTC */
117 #define CONFIG_RTC_DS1337
118 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
119 
120 /*
121  * Board NAND Info.
122  */
123 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
124 							/* to access nand */
125 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
126 							/* to access */
127 							/* nand at CS0 */
128 
129 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
130 							/* NAND devices */
131 #define CONFIG_JFFS2_NAND
132 /* nand device jffs2 lives on */
133 #define CONFIG_JFFS2_DEV		"nand0"
134 /* start of jffs2 partition */
135 #define CONFIG_JFFS2_PART_OFFSET	0x680000
136 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
137 
138 /* Environment information */
139 
140 #define CONFIG_BOOTFILE		"uImage"
141 
142 /* Setup MTD for NAND on the SOM */
143 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
144 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
145 				"1m(u-boot),256k(env1),"		\
146 				"256k(env2),6m(kernel),6m(k_recovery),"	\
147 				"8m(fs_recovery),-(common_data)"
148 
149 #define CONFIG_HOSTNAME mcx
150 #define CONFIG_EXTRA_ENV_SETTINGS \
151 	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
152 	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
153 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
154 	"addfb=setenv bootargs ${bootargs} vram=6M "			\
155 		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
156 	"addip_sta=setenv bootargs ${bootargs} "			\
157 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
158 		"${netmask}:${hostname}:eth0:off\0"			\
159 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
160 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
161 		"else run addip_sta;fi\0"				\
162 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
163 	"addtty=setenv bootargs ${bootargs} "				\
164 		"console=${consoledev},${baudrate}\0"			\
165 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
166 	"baudrate=115200\0"						\
167 	"consoledev=ttyO2\0"						\
168 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
169 	"loadaddr=0x82000000\0"						\
170 	"load=tftp ${loadaddr} ${u-boot}\0"				\
171 	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
172 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
173 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
174 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
175 	"mmcargs=root=/dev/mmcblk0p2 rw "				\
176 		"rootfstype=ext3 rootwait\0"				\
177 	"mmcboot=echo Booting from mmc ...; "				\
178 		"run mmcargs; "						\
179 		"run addip addtty addmtd addfb addeth addmisc;"		\
180 		"run loaduimage; "					\
181 		"bootm ${loadaddr}\0"					\
182 	"net_nfs=run load_k; "						\
183 		"run nfsargs; "						\
184 		"run addip addtty addmtd addfb addeth addmisc;"		\
185 		"bootm ${loadaddr}\0"					\
186 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
187 		"nfsroot=${serverip}:${rootpath}\0"			\
188 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
189 	"uboot_addr=0x80000\0"						\
190 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
191 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
192 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
193 		"nand write ${loadaddr} 0 20000\0"			\
194 	"upd=if run load;then echo Updating u-boot;if run update;"	\
195 		"then echo U-Boot updated;"				\
196 			"else echo Error updating u-boot !;"		\
197 			"echo Board without bootloader !!;"		\
198 		"fi;"							\
199 		"else echo U-Boot not downloaded..exiting;fi\0"		\
200 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
201 	"bootscript=echo Running bootscript from mmc ...; "		\
202 		"source ${loadaddr}\0"					\
203 	"nandargs=setenv bootargs ubi.mtd=7 "				\
204 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
205 	"nandboot=echo Booting from nand ...; "				\
206 		"run nandargs; "					\
207 		"ubi part nand0,4;"					\
208 		"ubi readvol ${loadaddr} kernel;"			\
209 		"run addtty addmtd addfb addeth addmisc;"		\
210 		"bootm ${loadaddr}\0"					\
211 	"preboot=ubi part nand0,7;"					\
212 		"ubi readvol ${loadaddr} splash;"			\
213 		"bmp display ${loadaddr};"				\
214 		"gpio set 55\0"						\
215 	"swupdate_args=setenv bootargs root=/dev/ram "			\
216 		"quiet loglevel=1 "					\
217 		"consoleblank=0 ${swupdate_misc}\0"			\
218 	"swupdate=echo Running Sw-Update...;"				\
219 		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
220 		"else mtdparts default;fi; "				\
221 		"ubi part nand0,5;"					\
222 		"ubi readvol 0x82000000 kernel_recovery;"		\
223 		"ubi part nand0,6;"					\
224 		"ubi readvol 0x84000000 fs_recovery;"			\
225 		"run swupdate_args; "					\
226 		"setenv bootargs ${bootargs} "				\
227 			"${mtdparts} "					\
228 			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
229 			"omapdss.def_disp=lcd;"				\
230 		"bootm 0x82000000 0x84000000\0"				\
231 	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
232 		"then source 82000000;else run nandboot;fi\0"
233 
234 #define CONFIG_AUTO_COMPLETE
235 #define CONFIG_CMDLINE_EDITING
236 
237 /*
238  * Miscellaneous configurable options
239  */
240 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
241 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
242 /* Print Buffer Size */
243 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
244 					sizeof(CONFIG_SYS_PROMPT) + 16)
245 #define CONFIG_SYS_MAXARGS		16	/* max number of command */
246 						/* args */
247 /* Boot Argument Buffer Size */
248 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
249 /* memtest works on */
250 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
251 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
252 					0x01F00000) /* 31MB */
253 
254 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
255 								/* address */
256 #define CONFIG_PREBOOT
257 
258 /*
259  * AM3517 has 12 GP timers, they can be driven by the system clock
260  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
261  * This rate is divided by a local divisor.
262  */
263 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
264 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
265 
266 /*
267  * Physical Memory Map
268  */
269 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
270 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
271 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
272 
273 /*
274  * FLASH and environment organization
275  */
276 
277 /* **** PISMO SUPPORT *** */
278 #define CONFIG_NAND
279 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
280 #define CONFIG_NAND_OMAP_GPMC
281 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
282 #define CONFIG_ENV_IS_IN_NAND
283 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
284 
285 /* Redundant Environment */
286 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
287 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
288 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
289 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
290 						2 * CONFIG_SYS_ENV_SECT_SIZE)
291 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
292 
293 /* Flash banks JFFS2 should use */
294 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
295 					CONFIG_SYS_MAX_NAND_DEVICE)
296 #define CONFIG_SYS_JFFS2_MEM_NAND
297 /* use flash_info[2] */
298 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
299 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
300 
301 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
302 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
303 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
304 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
305 					 CONFIG_SYS_INIT_RAM_SIZE - \
306 					 GENERATED_GBL_DATA_SIZE)
307 
308 /* Defines for SPL */
309 #define CONFIG_SPL_FRAMEWORK
310 #define CONFIG_SPL_BOARD_INIT
311 #define CONFIG_SPL_NAND_SIMPLE
312 
313 #define CONFIG_SPL_NAND_BASE
314 #define CONFIG_SPL_NAND_DRIVERS
315 #define CONFIG_SPL_NAND_ECC
316 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
317 
318 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
319 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
320 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
321 
322 /* move malloc and bss high to prevent clashing with the main image */
323 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
324 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
325 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
326 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
327 
328 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
329 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
330 
331 /* NAND boot config */
332 #define CONFIG_SYS_NAND_PAGE_COUNT	64
333 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
334 #define CONFIG_SYS_NAND_OOBSIZE		64
335 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
336 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
337 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
338 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
339 					 48, 49, 50, 51, 52, 53, 54, 55,\
340 					 56, 57, 58, 59, 60, 61, 62, 63}
341 #define CONFIG_SYS_NAND_ECCSIZE		256
342 #define CONFIG_SYS_NAND_ECCBYTES	3
343 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
344 #define CONFIG_SPL_NAND_SOFTECC
345 
346 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
347 
348 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
349 
350 /*
351  * ethernet support
352  *
353  */
354 #if defined(CONFIG_CMD_NET)
355 #define CONFIG_DRIVER_TI_EMAC
356 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
357 #define CONFIG_MII
358 #define CONFIG_BOOTP_DNS
359 #define CONFIG_BOOTP_DNS2
360 #define CONFIG_BOOTP_SEND_HOSTNAME
361 #define CONFIG_NET_RETRY_COUNT 10
362 #endif
363 
364 #define CONFIG_SPLASH_SCREEN
365 #define CONFIG_VIDEO_BMP_RLE8
366 #define CONFIG_CMD_BMP
367 #define CONFIG_VIDEO_OMAP3
368 
369 #endif /* __CONFIG_H */
370