1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 19 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 20 21 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 22 23 #include <asm/arch/cpu.h> /* get chip and board defs */ 24 #include <asm/arch/omap.h> 25 26 /* 27 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 28 * and older u-boot.bin with the new U-Boot SPL. 29 */ 30 #define CONFIG_SYS_TEXT_BASE 0x80008000 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 39 #define CONFIG_SETUP_MEMORY_TAGS 40 #define CONFIG_INITRD_TAG 41 #define CONFIG_REVISION_TAG 42 43 /* 44 * Size of malloc() pool 45 */ 46 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 47 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 48 /* 49 * DDR related 50 */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 61 62 #define CONFIG_SYS_NS16550_SERIAL 63 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 64 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 65 66 /* 67 * select serial console configuration 68 */ 69 #define CONFIG_CONS_INDEX 3 70 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 71 #define CONFIG_SERIAL3 3 /* UART3 */ 72 73 /* allow to overwrite serial and ethaddr */ 74 #define CONFIG_ENV_OVERWRITE 75 #define CONFIG_BAUDRATE 115200 76 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 77 115200} 78 79 /* EHCI */ 80 #define CONFIG_OMAP3_GPIO_2 81 #define CONFIG_OMAP3_GPIO_5 82 #define CONFIG_USB_EHCI 83 #define CONFIG_USB_EHCI_OMAP 84 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 85 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 86 #define CONFIG_USB_HOST_ETHER 87 #define CONFIG_USB_ETHER_ASIX 88 #define CONFIG_USB_ETHER_MCS7830 89 90 /* commands to include */ 91 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 92 93 #define CONFIG_CMD_DATE 94 #define CONFIG_CMD_NAND /* NAND support */ 95 #define CONFIG_CMD_UBIFS 96 #define CONFIG_RBTREE 97 #define CONFIG_LZO 98 #define CONFIG_MTD_PARTITIONS 99 #define CONFIG_MTD_DEVICE 100 #define CONFIG_CMD_MTDPARTS 101 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 104 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 105 #define CONFIG_SYS_I2C_OMAP34XX 106 107 /* RTC */ 108 #define CONFIG_RTC_DS1337 109 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 110 111 /* 112 * Board NAND Info. 113 */ 114 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 115 /* to access nand */ 116 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 117 /* to access */ 118 /* nand at CS0 */ 119 120 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 121 /* NAND devices */ 122 #define CONFIG_JFFS2_NAND 123 /* nand device jffs2 lives on */ 124 #define CONFIG_JFFS2_DEV "nand0" 125 /* start of jffs2 partition */ 126 #define CONFIG_JFFS2_PART_OFFSET 0x680000 127 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 128 129 /* Environment information */ 130 131 #define CONFIG_BOOTFILE "uImage" 132 133 /* Setup MTD for NAND on the SOM */ 134 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 135 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 136 "1m(u-boot),256k(env1)," \ 137 "256k(env2),6m(kernel),6m(k_recovery)," \ 138 "8m(fs_recovery),-(common_data)" 139 140 #define CONFIG_HOSTNAME mcx 141 #define CONFIG_EXTRA_ENV_SETTINGS \ 142 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 143 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 144 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 145 "addfb=setenv bootargs ${bootargs} vram=6M " \ 146 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 147 "addip_sta=setenv bootargs ${bootargs} " \ 148 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 149 "${netmask}:${hostname}:eth0:off\0" \ 150 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 151 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 152 "else run addip_sta;fi\0" \ 153 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 154 "addtty=setenv bootargs ${bootargs} " \ 155 "console=${consoledev},${baudrate}\0" \ 156 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 157 "baudrate=115200\0" \ 158 "consoledev=ttyO2\0" \ 159 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 160 "loadaddr=0x82000000\0" \ 161 "load=tftp ${loadaddr} ${u-boot}\0" \ 162 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 163 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 164 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 165 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 166 "mmcargs=root=/dev/mmcblk0p2 rw " \ 167 "rootfstype=ext3 rootwait\0" \ 168 "mmcboot=echo Booting from mmc ...; " \ 169 "run mmcargs; " \ 170 "run addip addtty addmtd addfb addeth addmisc;" \ 171 "run loaduimage; " \ 172 "bootm ${loadaddr}\0" \ 173 "net_nfs=run load_k; " \ 174 "run nfsargs; " \ 175 "run addip addtty addmtd addfb addeth addmisc;" \ 176 "bootm ${loadaddr}\0" \ 177 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 178 "nfsroot=${serverip}:${rootpath}\0" \ 179 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 180 "uboot_addr=0x80000\0" \ 181 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 182 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 183 "updatemlo=nandecc hw;nand erase 0 20000;" \ 184 "nand write ${loadaddr} 0 20000\0" \ 185 "upd=if run load;then echo Updating u-boot;if run update;" \ 186 "then echo U-Boot updated;" \ 187 "else echo Error updating u-boot !;" \ 188 "echo Board without bootloader !!;" \ 189 "fi;" \ 190 "else echo U-Boot not downloaded..exiting;fi\0" \ 191 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 192 "bootscript=echo Running bootscript from mmc ...; " \ 193 "source ${loadaddr}\0" \ 194 "nandargs=setenv bootargs ubi.mtd=7 " \ 195 "root=ubi0:rootfs rootfstype=ubifs\0" \ 196 "nandboot=echo Booting from nand ...; " \ 197 "run nandargs; " \ 198 "ubi part nand0,4;" \ 199 "ubi readvol ${loadaddr} kernel;" \ 200 "run addtty addmtd addfb addeth addmisc;" \ 201 "bootm ${loadaddr}\0" \ 202 "preboot=ubi part nand0,7;" \ 203 "ubi readvol ${loadaddr} splash;" \ 204 "bmp display ${loadaddr};" \ 205 "gpio set 55\0" \ 206 "swupdate_args=setenv bootargs root=/dev/ram " \ 207 "quiet loglevel=1 " \ 208 "consoleblank=0 ${swupdate_misc}\0" \ 209 "swupdate=echo Running Sw-Update...;" \ 210 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 211 "else mtdparts default;fi; " \ 212 "ubi part nand0,5;" \ 213 "ubi readvol 0x82000000 kernel_recovery;" \ 214 "ubi part nand0,6;" \ 215 "ubi readvol 0x84000000 fs_recovery;" \ 216 "run swupdate_args; " \ 217 "setenv bootargs ${bootargs} " \ 218 "${mtdparts} " \ 219 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 220 "omapdss.def_disp=lcd;" \ 221 "bootm 0x82000000 0x84000000\0" \ 222 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 223 "then source 82000000;else run nandboot;fi\0" 224 225 #define CONFIG_AUTO_COMPLETE 226 #define CONFIG_CMDLINE_EDITING 227 228 /* 229 * Miscellaneous configurable options 230 */ 231 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 232 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 233 /* Print Buffer Size */ 234 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 235 sizeof(CONFIG_SYS_PROMPT) + 16) 236 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 237 /* args */ 238 /* Boot Argument Buffer Size */ 239 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 240 /* memtest works on */ 241 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 242 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 243 0x01F00000) /* 31MB */ 244 245 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 246 /* address */ 247 #define CONFIG_PREBOOT 248 249 /* 250 * AM3517 has 12 GP timers, they can be driven by the system clock 251 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 252 * This rate is divided by a local divisor. 253 */ 254 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 255 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 256 257 /* 258 * Physical Memory Map 259 */ 260 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 261 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 262 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 263 264 /* 265 * FLASH and environment organization 266 */ 267 268 /* **** PISMO SUPPORT *** */ 269 #define CONFIG_NAND 270 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 271 #define CONFIG_NAND_OMAP_GPMC 272 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 273 #define CONFIG_ENV_IS_IN_NAND 274 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 275 276 /* Redundant Environment */ 277 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 278 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 279 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 280 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 281 2 * CONFIG_SYS_ENV_SECT_SIZE) 282 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 283 284 /* Flash banks JFFS2 should use */ 285 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 286 CONFIG_SYS_MAX_NAND_DEVICE) 287 #define CONFIG_SYS_JFFS2_MEM_NAND 288 /* use flash_info[2] */ 289 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 290 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 291 292 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 293 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 294 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 295 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 296 CONFIG_SYS_INIT_RAM_SIZE - \ 297 GENERATED_GBL_DATA_SIZE) 298 299 /* Defines for SPL */ 300 #define CONFIG_SPL_FRAMEWORK 301 #define CONFIG_SPL_BOARD_INIT 302 #define CONFIG_SPL_NAND_SIMPLE 303 304 #define CONFIG_SPL_NAND_BASE 305 #define CONFIG_SPL_NAND_DRIVERS 306 #define CONFIG_SPL_NAND_ECC 307 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 308 309 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 310 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 311 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 312 313 /* move malloc and bss high to prevent clashing with the main image */ 314 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 315 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 316 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 317 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 318 319 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 320 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 321 322 /* NAND boot config */ 323 #define CONFIG_SYS_NAND_PAGE_COUNT 64 324 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 325 #define CONFIG_SYS_NAND_OOBSIZE 64 326 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 327 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 328 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 329 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 330 48, 49, 50, 51, 52, 53, 54, 55,\ 331 56, 57, 58, 59, 60, 61, 62, 63} 332 #define CONFIG_SYS_NAND_ECCSIZE 256 333 #define CONFIG_SYS_NAND_ECCBYTES 3 334 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 335 #define CONFIG_SPL_NAND_SOFTECC 336 337 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 338 339 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 340 341 /* 342 * ethernet support 343 * 344 */ 345 #if defined(CONFIG_CMD_NET) 346 #define CONFIG_DRIVER_TI_EMAC 347 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 348 #define CONFIG_MII 349 #define CONFIG_BOOTP_DNS 350 #define CONFIG_BOOTP_DNS2 351 #define CONFIG_BOOTP_SEND_HOSTNAME 352 #define CONFIG_NET_RETRY_COUNT 10 353 #endif 354 355 #define CONFIG_SPLASH_SCREEN 356 #define CONFIG_VIDEO_BMP_RLE8 357 #define CONFIG_CMD_BMP 358 #define CONFIG_VIDEO_OMAP3 359 360 #endif /* __CONFIG_H */ 361