xref: /openbmc/u-boot/include/configs/mcx.h (revision 4de512018ba7d57f1672be21c7459281f7c97514)
1 /*
2  * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3  *
4  * Based on omap3_evm_config.h
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 
16 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
17 
18 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
19 
20 #include <asm/arch/cpu.h>		/* get chip and board defs */
21 #include <asm/arch/omap.h>
22 
23 /*
24  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
25  * and older u-boot.bin with the new U-Boot SPL.
26  */
27 #define CONFIG_SYS_TEXT_BASE		0x80008000
28 
29 /* Clock Defines */
30 #define V_OSCK			26000000	/* Clock output from T2 */
31 #define V_SCLK			(V_OSCK >> 1)
32 
33 #define CONFIG_MISC_INIT_R
34 
35 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
39 
40 /*
41  * Size of malloc() pool
42  */
43 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
44 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
45 /*
46  * DDR related
47  */
48 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
49 
50 /*
51  * Hardware drivers
52  */
53 
54 /*
55  * NS16550 Configuration
56  */
57 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
58 
59 #define CONFIG_SYS_NS16550_SERIAL
60 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
61 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
62 
63 /*
64  * select serial console configuration
65  */
66 #define CONFIG_CONS_INDEX		3
67 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
68 #define CONFIG_SERIAL3			3	/* UART3 */
69 
70 /* allow to overwrite serial and ethaddr */
71 #define CONFIG_ENV_OVERWRITE
72 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
73 					115200}
74 
75 /* EHCI */
76 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
77 #define	CONFIG_USB_HOST_ETHER
78 #define	CONFIG_USB_ETHER_ASIX
79 #define CONFIG_USB_ETHER_MCS7830
80 
81 /* commands to include */
82 
83 #define CONFIG_CMD_NAND		/* NAND support			*/
84 #define CONFIG_MTD_PARTITIONS
85 #define CONFIG_MTD_DEVICE
86 
87 #define CONFIG_SYS_I2C
88 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
89 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
90 #define CONFIG_SYS_I2C_OMAP34XX
91 
92 /* RTC */
93 #define CONFIG_RTC_DS1337
94 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
95 
96 /*
97  * Board NAND Info.
98  */
99 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
100 							/* to access nand */
101 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
102 							/* to access */
103 							/* nand at CS0 */
104 
105 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
106 							/* NAND devices */
107 #define CONFIG_JFFS2_NAND
108 /* nand device jffs2 lives on */
109 #define CONFIG_JFFS2_DEV		"nand0"
110 /* start of jffs2 partition */
111 #define CONFIG_JFFS2_PART_OFFSET	0x680000
112 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
113 
114 /* Environment information */
115 
116 #define CONFIG_BOOTFILE		"uImage"
117 
118 /* Setup MTD for NAND on the SOM */
119 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
120 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
121 				"1m(u-boot),256k(env1),"		\
122 				"256k(env2),6m(kernel),6m(k_recovery),"	\
123 				"8m(fs_recovery),-(common_data)"
124 
125 #define CONFIG_HOSTNAME mcx
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127 	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
128 	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
129 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
130 	"addfb=setenv bootargs ${bootargs} vram=6M "			\
131 		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
132 	"addip_sta=setenv bootargs ${bootargs} "			\
133 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
134 		"${netmask}:${hostname}:eth0:off\0"			\
135 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
136 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
137 		"else run addip_sta;fi\0"				\
138 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
139 	"addtty=setenv bootargs ${bootargs} "				\
140 		"console=${consoledev},${baudrate}\0"			\
141 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
142 	"baudrate=115200\0"						\
143 	"consoledev=ttyO2\0"						\
144 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
145 	"loadaddr=0x82000000\0"						\
146 	"load=tftp ${loadaddr} ${u-boot}\0"				\
147 	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
148 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
149 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
150 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
151 	"mmcargs=root=/dev/mmcblk0p2 rw "				\
152 		"rootfstype=ext3 rootwait\0"				\
153 	"mmcboot=echo Booting from mmc ...; "				\
154 		"run mmcargs; "						\
155 		"run addip addtty addmtd addfb addeth addmisc;"		\
156 		"run loaduimage; "					\
157 		"bootm ${loadaddr}\0"					\
158 	"net_nfs=run load_k; "						\
159 		"run nfsargs; "						\
160 		"run addip addtty addmtd addfb addeth addmisc;"		\
161 		"bootm ${loadaddr}\0"					\
162 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
163 		"nfsroot=${serverip}:${rootpath}\0"			\
164 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
165 	"uboot_addr=0x80000\0"						\
166 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
167 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
168 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
169 		"nand write ${loadaddr} 0 20000\0"			\
170 	"upd=if run load;then echo Updating u-boot;if run update;"	\
171 		"then echo U-Boot updated;"				\
172 			"else echo Error updating u-boot !;"		\
173 			"echo Board without bootloader !!;"		\
174 		"fi;"							\
175 		"else echo U-Boot not downloaded..exiting;fi\0"		\
176 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
177 	"bootscript=echo Running bootscript from mmc ...; "		\
178 		"source ${loadaddr}\0"					\
179 	"nandargs=setenv bootargs ubi.mtd=7 "				\
180 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
181 	"nandboot=echo Booting from nand ...; "				\
182 		"run nandargs; "					\
183 		"ubi part nand0,4;"					\
184 		"ubi readvol ${loadaddr} kernel;"			\
185 		"run addtty addmtd addfb addeth addmisc;"		\
186 		"bootm ${loadaddr}\0"					\
187 	"preboot=ubi part nand0,7;"					\
188 		"ubi readvol ${loadaddr} splash;"			\
189 		"bmp display ${loadaddr};"				\
190 		"gpio set 55\0"						\
191 	"swupdate_args=setenv bootargs root=/dev/ram "			\
192 		"quiet loglevel=1 "					\
193 		"consoleblank=0 ${swupdate_misc}\0"			\
194 	"swupdate=echo Running Sw-Update...;"				\
195 		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
196 		"else mtdparts default;fi; "				\
197 		"ubi part nand0,5;"					\
198 		"ubi readvol 0x82000000 kernel_recovery;"		\
199 		"ubi part nand0,6;"					\
200 		"ubi readvol 0x84000000 fs_recovery;"			\
201 		"run swupdate_args; "					\
202 		"setenv bootargs ${bootargs} "				\
203 			"${mtdparts} "					\
204 			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
205 			"omapdss.def_disp=lcd;"				\
206 		"bootm 0x82000000 0x84000000\0"				\
207 	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
208 		"then source 82000000;else run nandboot;fi\0"
209 
210 #define CONFIG_AUTO_COMPLETE
211 #define CONFIG_CMDLINE_EDITING
212 
213 /*
214  * Miscellaneous configurable options
215  */
216 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
217 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
218 /* Print Buffer Size */
219 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
220 					sizeof(CONFIG_SYS_PROMPT) + 16)
221 #define CONFIG_SYS_MAXARGS		16	/* max number of command */
222 						/* args */
223 /* Boot Argument Buffer Size */
224 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
225 /* memtest works on */
226 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
227 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
228 					0x01F00000) /* 31MB */
229 
230 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
231 								/* address */
232 #define CONFIG_PREBOOT
233 
234 /*
235  * AM3517 has 12 GP timers, they can be driven by the system clock
236  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
237  * This rate is divided by a local divisor.
238  */
239 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
240 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
241 
242 /*
243  * Physical Memory Map
244  */
245 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
246 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
247 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
248 
249 /*
250  * FLASH and environment organization
251  */
252 
253 /* **** PISMO SUPPORT *** */
254 #define CONFIG_NAND
255 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
256 #define CONFIG_NAND_OMAP_GPMC
257 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
258 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
259 
260 /* Redundant Environment */
261 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
262 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
263 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
264 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
265 						2 * CONFIG_SYS_ENV_SECT_SIZE)
266 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
267 
268 /* Flash banks JFFS2 should use */
269 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
270 					CONFIG_SYS_MAX_NAND_DEVICE)
271 #define CONFIG_SYS_JFFS2_MEM_NAND
272 /* use flash_info[2] */
273 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
274 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
275 
276 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
277 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
278 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
279 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
280 					 CONFIG_SYS_INIT_RAM_SIZE - \
281 					 GENERATED_GBL_DATA_SIZE)
282 
283 /* Defines for SPL */
284 #define CONFIG_SPL_FRAMEWORK
285 #define CONFIG_SPL_NAND_SIMPLE
286 
287 #define CONFIG_SPL_NAND_BASE
288 #define CONFIG_SPL_NAND_DRIVERS
289 #define CONFIG_SPL_NAND_ECC
290 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
291 
292 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
293 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
294 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
295 
296 /* move malloc and bss high to prevent clashing with the main image */
297 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
298 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
299 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
300 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
301 
302 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
303 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
304 
305 /* NAND boot config */
306 #define CONFIG_SYS_NAND_PAGE_COUNT	64
307 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
308 #define CONFIG_SYS_NAND_OOBSIZE		64
309 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
310 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
311 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
312 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
313 					 48, 49, 50, 51, 52, 53, 54, 55,\
314 					 56, 57, 58, 59, 60, 61, 62, 63}
315 #define CONFIG_SYS_NAND_ECCSIZE		256
316 #define CONFIG_SYS_NAND_ECCBYTES	3
317 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
318 #define CONFIG_SPL_NAND_SOFTECC
319 
320 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
321 
322 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
323 
324 /*
325  * ethernet support
326  *
327  */
328 #if defined(CONFIG_CMD_NET)
329 #define CONFIG_DRIVER_TI_EMAC
330 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
331 #define CONFIG_MII
332 #define CONFIG_BOOTP_DNS
333 #define CONFIG_BOOTP_DNS2
334 #define CONFIG_BOOTP_SEND_HOSTNAME
335 #define CONFIG_NET_RETRY_COUNT 10
336 #endif
337 
338 #define CONFIG_SPLASH_SCREEN
339 #define CONFIG_VIDEO_BMP_RLE8
340 #define CONFIG_VIDEO_OMAP3
341 
342 #endif /* __CONFIG_H */
343