xref: /openbmc/u-boot/include/configs/mcx.h (revision 24b852a7a2b8eca71789100983bdb5104cc00696)
1 /*
2  * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3  *
4  * Based on omap3_evm_config.h
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_OMAP			/* in a TI OMAP core */
16 #define CONFIG_OMAP3_MCX		/* working with mcx */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23 
24 #define MACH_TYPE_MCX			3656
25 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
26 #define CONFIG_BOARD_LATE_INIT
27 
28 
29 #define CONFIG_SYS_CACHELINE_SIZE	64
30 
31 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
32 
33 #include <asm/arch/cpu.h>		/* get chip and board defs */
34 #include <asm/arch/omap.h>
35 
36 #define CONFIG_OF_LIBFDT
37 #define CONFIG_FIT
38 
39 /*
40  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
41  * and older u-boot.bin with the new U-Boot SPL.
42  */
43 #define CONFIG_SYS_TEXT_BASE		0x80008000
44 
45 /*
46  * Display CPU and Board information
47  */
48 #define CONFIG_DISPLAY_CPUINFO
49 #define CONFIG_DISPLAY_BOARDINFO
50 
51 /* Clock Defines */
52 #define V_OSCK			26000000	/* Clock output from T2 */
53 #define V_SCLK			(V_OSCK >> 1)
54 
55 #define CONFIG_MISC_INIT_R
56 
57 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS
59 #define CONFIG_INITRD_TAG
60 #define CONFIG_REVISION_TAG
61 
62 /*
63  * Size of malloc() pool
64  */
65 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
66 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
67 /*
68  * DDR related
69  */
70 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
71 
72 /*
73  * Hardware drivers
74  */
75 
76 /*
77  * NS16550 Configuration
78  */
79 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
80 
81 #define CONFIG_SYS_NS16550
82 #define CONFIG_SYS_NS16550_SERIAL
83 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
84 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
85 
86 /*
87  * select serial console configuration
88  */
89 #define CONFIG_CONS_INDEX		3
90 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
91 #define CONFIG_SERIAL3			3	/* UART3 */
92 
93 /* allow to overwrite serial and ethaddr */
94 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_BAUDRATE			115200
96 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
97 					115200}
98 #define CONFIG_MMC
99 #define CONFIG_OMAP_HSMMC
100 #define CONFIG_GENERIC_MMC
101 #define CONFIG_DOS_PARTITION
102 
103 /* EHCI */
104 #define CONFIG_USB_STORAGE
105 #define CONFIG_OMAP3_GPIO_2
106 #define CONFIG_OMAP3_GPIO_5
107 #define CONFIG_USB_EHCI
108 #define CONFIG_USB_EHCI_OMAP
109 #define CONFIG_USB_ULPI
110 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
111 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
112 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
113 #define	CONFIG_USB_HOST_ETHER
114 #define	CONFIG_USB_ETHER_ASIX
115 #define CONFIG_USB_ETHER_MCS7830
116 
117 /* commands to include */
118 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
119 #define CONFIG_CMD_FAT		/* FAT support			*/
120 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
121 
122 #define CONFIG_CMD_DATE
123 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
124 #define CONFIG_CMD_MMC		/* MMC support			*/
125 #define CONFIG_CMD_FAT		/* FAT support			*/
126 #define CONFIG_CMD_USB
127 #define CONFIG_CMD_NAND		/* NAND support			*/
128 #define CONFIG_CMD_DHCP
129 #define CONFIG_CMD_PING
130 #define CONFIG_CMD_CACHE
131 #define CONFIG_CMD_UBI
132 #define CONFIG_CMD_UBIFS
133 #define CONFIG_RBTREE
134 #define CONFIG_LZO
135 #define CONFIG_MTD_PARTITIONS
136 #define CONFIG_MTD_DEVICE
137 #define CONFIG_CMD_MTDPARTS
138 
139 #define CONFIG_SYS_NO_FLASH
140 #define CONFIG_SYS_I2C
141 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
142 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
143 #define CONFIG_SYS_I2C_OMAP34XX
144 
145 /* RTC */
146 #define CONFIG_RTC_DS1337
147 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
148 
149 #define CONFIG_CMD_MII
150 /*
151  * Board NAND Info.
152  */
153 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
154 							/* to access nand */
155 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
156 							/* to access */
157 							/* nand at CS0 */
158 
159 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
160 							/* NAND devices */
161 #define CONFIG_JFFS2_NAND
162 /* nand device jffs2 lives on */
163 #define CONFIG_JFFS2_DEV		"nand0"
164 /* start of jffs2 partition */
165 #define CONFIG_JFFS2_PART_OFFSET	0x680000
166 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
167 
168 /* Environment information */
169 #define CONFIG_BOOTDELAY	3
170 
171 #define CONFIG_BOOTFILE		"uImage"
172 
173 /* Setup MTD for NAND on the SOM */
174 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
175 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
176 				"1m(u-boot),256k(env1),"		\
177 				"256k(env2),6m(kernel),6m(k_recovery),"	\
178 				"8m(fs_recovery),-(common_data)"
179 
180 #define CONFIG_HOSTNAME mcx
181 #define CONFIG_EXTRA_ENV_SETTINGS \
182 	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
183 	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
184 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
185 	"addfb=setenv bootargs ${bootargs} vram=6M "			\
186 		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
187 	"addip_sta=setenv bootargs ${bootargs} "			\
188 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
189 		"${netmask}:${hostname}:eth0:off\0"			\
190 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
191 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
192 		"else run addip_sta;fi\0"				\
193 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
194 	"addtty=setenv bootargs ${bootargs} "				\
195 		"console=${consoledev},${baudrate}\0"			\
196 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
197 	"baudrate=115200\0"						\
198 	"consoledev=ttyO2\0"						\
199 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
200 	"loadaddr=0x82000000\0"						\
201 	"load=tftp ${loadaddr} ${u-boot}\0"				\
202 	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
203 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
204 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
205 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
206 	"mmcargs=root=/dev/mmcblk0p2 rw "				\
207 		"rootfstype=ext3 rootwait\0"				\
208 	"mmcboot=echo Booting from mmc ...; "				\
209 		"run mmcargs; "						\
210 		"run addip addtty addmtd addfb addeth addmisc;"		\
211 		"run loaduimage; "					\
212 		"bootm ${loadaddr}\0"					\
213 	"net_nfs=run load_k; "						\
214 		"run nfsargs; "						\
215 		"run addip addtty addmtd addfb addeth addmisc;"		\
216 		"bootm ${loadaddr}\0"					\
217 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
218 		"nfsroot=${serverip}:${rootpath}\0"			\
219 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
220 	"uboot_addr=0x80000\0"						\
221 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
222 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
223 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
224 		"nand write ${loadaddr} 0 20000\0"			\
225 	"upd=if run load;then echo Updating u-boot;if run update;"	\
226 		"then echo U-Boot updated;"				\
227 			"else echo Error updating u-boot !;"		\
228 			"echo Board without bootloader !!;"		\
229 		"fi;"							\
230 		"else echo U-Boot not downloaded..exiting;fi\0"		\
231 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
232 	"bootscript=echo Running bootscript from mmc ...; "		\
233 		"source ${loadaddr}\0"					\
234 	"nandargs=setenv bootargs ubi.mtd=7 "				\
235 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
236 	"nandboot=echo Booting from nand ...; "				\
237 		"run nandargs; "					\
238 		"ubi part nand0,4;"					\
239 		"ubi readvol ${loadaddr} kernel;"			\
240 		"run addtty addmtd addfb addeth addmisc;"		\
241 		"bootm ${loadaddr}\0"					\
242 	"preboot=ubi part nand0,7;"					\
243 		"ubi readvol ${loadaddr} splash;"			\
244 		"bmp display ${loadaddr};"				\
245 		"gpio set 55\0"						\
246 	"swupdate_args=setenv bootargs root=/dev/ram "			\
247 		"quiet loglevel=1 "					\
248 		"consoleblank=0 ${swupdate_misc}\0"			\
249 	"swupdate=echo Running Sw-Update...;"				\
250 		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
251 		"else mtdparts default;fi; "				\
252 		"ubi part nand0,5;"					\
253 		"ubi readvol 0x82000000 kernel_recovery;"		\
254 		"ubi part nand0,6;"					\
255 		"ubi readvol 0x84000000 fs_recovery;"			\
256 		"run swupdate_args; "					\
257 		"setenv bootargs ${bootargs} "				\
258 			"${mtdparts} "					\
259 			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
260 			"omapdss.def_disp=lcd;"				\
261 		"bootm 0x82000000 0x84000000\0"				\
262 	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
263 		"then source 82000000;else run nandboot;fi\0"
264 
265 #define CONFIG_AUTO_COMPLETE
266 #define CONFIG_CMDLINE_EDITING
267 
268 /*
269  * Miscellaneous configurable options
270  */
271 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
272 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
273 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
274 /* Print Buffer Size */
275 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
276 					sizeof(CONFIG_SYS_PROMPT) + 16)
277 #define CONFIG_SYS_MAXARGS		16	/* max number of command */
278 						/* args */
279 /* Boot Argument Buffer Size */
280 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
281 /* memtest works on */
282 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
283 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
284 					0x01F00000) /* 31MB */
285 
286 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
287 								/* address */
288 #define CONFIG_PREBOOT
289 
290 /*
291  * AM3517 has 12 GP timers, they can be driven by the system clock
292  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
293  * This rate is divided by a local divisor.
294  */
295 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
296 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
297 
298 /*
299  * Physical Memory Map
300  */
301 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
302 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
303 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
304 
305 /*
306  * FLASH and environment organization
307  */
308 
309 /* **** PISMO SUPPORT *** */
310 #define CONFIG_NAND
311 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
312 #define CONFIG_NAND_OMAP_GPMC
313 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
314 #define CONFIG_ENV_IS_IN_NAND
315 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
316 
317 /* Redundant Environment */
318 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
319 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
320 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
321 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
322 						2 * CONFIG_SYS_ENV_SECT_SIZE)
323 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
324 
325 /* Flash banks JFFS2 should use */
326 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
327 					CONFIG_SYS_MAX_NAND_DEVICE)
328 #define CONFIG_SYS_JFFS2_MEM_NAND
329 /* use flash_info[2] */
330 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
331 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
332 
333 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
334 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
335 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
336 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
337 					 CONFIG_SYS_INIT_RAM_SIZE - \
338 					 GENERATED_GBL_DATA_SIZE)
339 
340 /* Defines for SPL */
341 #define CONFIG_SPL_FRAMEWORK
342 #define CONFIG_SPL_BOARD_INIT
343 #define CONFIG_SPL_NAND_SIMPLE
344 
345 #define CONFIG_SPL_LIBCOMMON_SUPPORT
346 #define CONFIG_SPL_LIBDISK_SUPPORT
347 #define CONFIG_SPL_I2C_SUPPORT
348 #define CONFIG_SPL_MMC_SUPPORT
349 #define CONFIG_SPL_FAT_SUPPORT
350 #define CONFIG_SPL_LIBGENERIC_SUPPORT
351 #define CONFIG_SPL_SERIAL_SUPPORT
352 #define CONFIG_SPL_POWER_SUPPORT
353 #define CONFIG_SPL_NAND_SUPPORT
354 #define CONFIG_SPL_NAND_BASE
355 #define CONFIG_SPL_NAND_DRIVERS
356 #define CONFIG_SPL_NAND_ECC
357 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
358 
359 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
360 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
361 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
362 
363 /* move malloc and bss high to prevent clashing with the main image */
364 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
365 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
366 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
367 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
368 
369 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
370 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
371 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
372 
373 /* NAND boot config */
374 #define CONFIG_SYS_NAND_PAGE_COUNT	64
375 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
376 #define CONFIG_SYS_NAND_OOBSIZE		64
377 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
378 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
379 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
380 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
381 					 48, 49, 50, 51, 52, 53, 54, 55,\
382 					 56, 57, 58, 59, 60, 61, 62, 63}
383 #define CONFIG_SYS_NAND_ECCSIZE		256
384 #define CONFIG_SYS_NAND_ECCBYTES	3
385 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
386 #define CONFIG_SPL_NAND_SOFTECC
387 
388 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
389 
390 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
391 
392 /*
393  * ethernet support
394  *
395  */
396 #if defined(CONFIG_CMD_NET)
397 #define CONFIG_DRIVER_TI_EMAC
398 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
399 #define CONFIG_MII
400 #define CONFIG_BOOTP_DNS
401 #define CONFIG_BOOTP_DNS2
402 #define CONFIG_BOOTP_SEND_HOSTNAME
403 #define CONFIG_NET_RETRY_COUNT 10
404 #endif
405 
406 #define CONFIG_VIDEO
407 #define CONFIG_CFB_CONSOLE
408 #define CONFIG_VGA_AS_SINGLE_DEVICE
409 #define CONFIG_SPLASH_SCREEN
410 #define CONFIG_VIDEO_BMP_RLE8
411 #define CONFIG_CMD_BMP
412 #define CONFIG_VIDEO_OMAP3
413 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
414 
415 #endif /* __CONFIG_H */
416