1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 4 * 5 * Based on omap3_evm_config.h 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 15 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 16 17 #include <asm/arch/cpu.h> /* get chip and board defs */ 18 #include <asm/arch/omap.h> 19 20 /* 21 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 22 * and older u-boot.bin with the new U-Boot SPL. 23 */ 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_REVISION_TAG 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 38 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 39 /* 40 * DDR related 41 */ 42 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 43 44 /* 45 * Hardware drivers 46 */ 47 48 /* 49 * NS16550 Configuration 50 */ 51 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 52 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 56 57 /* 58 * select serial console configuration 59 */ 60 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 61 62 /* allow to overwrite serial and ethaddr */ 63 #define CONFIG_ENV_OVERWRITE 64 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 65 115200} 66 67 /* EHCI */ 68 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 69 70 /* commands to include */ 71 72 #define CONFIG_SYS_I2C 73 74 /* RTC */ 75 #define CONFIG_RTC_DS1337 76 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 77 78 /* 79 * Board NAND Info. 80 */ 81 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 82 /* to access */ 83 /* nand at CS0 */ 84 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 86 /* NAND devices */ 87 #define CONFIG_JFFS2_NAND 88 /* nand device jffs2 lives on */ 89 #define CONFIG_JFFS2_DEV "nand0" 90 /* start of jffs2 partition */ 91 #define CONFIG_JFFS2_PART_OFFSET 0x680000 92 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 93 94 /* Environment information */ 95 96 #define CONFIG_BOOTFILE "uImage" 97 98 /* Setup MTD for NAND on the SOM */ 99 100 #define CONFIG_HOSTNAME "mcx" 101 #define CONFIG_EXTRA_ENV_SETTINGS \ 102 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 103 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 104 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 105 "addfb=setenv bootargs ${bootargs} vram=6M " \ 106 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 107 "addip_sta=setenv bootargs ${bootargs} " \ 108 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 109 "${netmask}:${hostname}:eth0:off\0" \ 110 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 111 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 112 "else run addip_sta;fi\0" \ 113 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 114 "addtty=setenv bootargs ${bootargs} " \ 115 "console=${consoledev},${baudrate}\0" \ 116 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 117 "baudrate=115200\0" \ 118 "consoledev=ttyO2\0" \ 119 "hostname=" CONFIG_HOSTNAME "\0" \ 120 "loadaddr=0x82000000\0" \ 121 "load=tftp ${loadaddr} ${u-boot}\0" \ 122 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 123 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 124 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 125 "mlo=" CONFIG_HOSTNAME "/MLO\0" \ 126 "mmcargs=root=/dev/mmcblk0p2 rw " \ 127 "rootfstype=ext3 rootwait\0" \ 128 "mmcboot=echo Booting from mmc ...; " \ 129 "run mmcargs; " \ 130 "run addip addtty addmtd addfb addeth addmisc;" \ 131 "run loaduimage; " \ 132 "bootm ${loadaddr}\0" \ 133 "net_nfs=run load_k; " \ 134 "run nfsargs; " \ 135 "run addip addtty addmtd addfb addeth addmisc;" \ 136 "bootm ${loadaddr}\0" \ 137 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 138 "nfsroot=${serverip}:${rootpath}\0" \ 139 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ 140 "uboot_addr=0x80000\0" \ 141 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 142 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 143 "updatemlo=nandecc hw;nand erase 0 20000;" \ 144 "nand write ${loadaddr} 0 20000\0" \ 145 "upd=if run load;then echo Updating u-boot;if run update;" \ 146 "then echo U-Boot updated;" \ 147 "else echo Error updating u-boot !;" \ 148 "echo Board without bootloader !!;" \ 149 "fi;" \ 150 "else echo U-Boot not downloaded..exiting;fi\0" \ 151 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 152 "bootscript=echo Running bootscript from mmc ...; " \ 153 "source ${loadaddr}\0" \ 154 "nandargs=setenv bootargs ubi.mtd=7 " \ 155 "root=ubi0:rootfs rootfstype=ubifs\0" \ 156 "nandboot=echo Booting from nand ...; " \ 157 "run nandargs; " \ 158 "ubi part nand0,4;" \ 159 "ubi readvol ${loadaddr} kernel;" \ 160 "run addtty addmtd addfb addeth addmisc;" \ 161 "bootm ${loadaddr}\0" \ 162 "preboot=ubi part nand0,7;" \ 163 "ubi readvol ${loadaddr} splash;" \ 164 "bmp display ${loadaddr};" \ 165 "gpio set 55\0" \ 166 "swupdate_args=setenv bootargs root=/dev/ram " \ 167 "quiet loglevel=1 " \ 168 "consoleblank=0 ${swupdate_misc}\0" \ 169 "swupdate=echo Running Sw-Update...;" \ 170 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 171 "else mtdparts default;fi; " \ 172 "ubi part nand0,5;" \ 173 "ubi readvol 0x82000000 kernel_recovery;" \ 174 "ubi part nand0,6;" \ 175 "ubi readvol 0x84000000 fs_recovery;" \ 176 "run swupdate_args; " \ 177 "setenv bootargs ${bootargs} " \ 178 "${mtdparts} " \ 179 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 180 "omapdss.def_disp=lcd;" \ 181 "bootm 0x82000000 0x84000000\0" \ 182 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 183 "then source 82000000;else run nandboot;fi\0" 184 185 /* 186 * Miscellaneous configurable options 187 */ 188 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 189 /* Boot Argument Buffer Size */ 190 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 191 /* memtest works on */ 192 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 193 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 194 0x01F00000) /* 31MB */ 195 196 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 197 /* address */ 198 #define CONFIG_PREBOOT 199 200 /* 201 * AM3517 has 12 GP timers, they can be driven by the system clock 202 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 203 * This rate is divided by a local divisor. 204 */ 205 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 206 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 207 208 /* 209 * Physical Memory Map 210 */ 211 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 212 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 213 214 /* 215 * FLASH and environment organization 216 */ 217 218 /* **** PISMO SUPPORT *** */ 219 220 /* Redundant Environment */ 221 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 222 #define CONFIG_ENV_OFFSET 0x180000 223 #define CONFIG_ENV_ADDR 0x180000 224 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 225 2 * CONFIG_SYS_ENV_SECT_SIZE) 226 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 227 228 /* Flash banks JFFS2 should use */ 229 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 230 CONFIG_SYS_MAX_NAND_DEVICE) 231 #define CONFIG_SYS_JFFS2_MEM_NAND 232 /* use flash_info[2] */ 233 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 234 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 235 236 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 237 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 238 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 239 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 240 CONFIG_SYS_INIT_RAM_SIZE - \ 241 GENERATED_GBL_DATA_SIZE) 242 243 /* Defines for SPL */ 244 245 #define CONFIG_SPL_NAND_BASE 246 #define CONFIG_SPL_NAND_DRIVERS 247 #define CONFIG_SPL_NAND_ECC 248 249 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 250 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 251 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 252 253 /* move malloc and bss high to prevent clashing with the main image */ 254 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 255 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 256 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 257 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 258 259 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 260 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 261 262 /* NAND boot config */ 263 #define CONFIG_SYS_NAND_PAGE_COUNT 64 264 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 265 #define CONFIG_SYS_NAND_OOBSIZE 64 266 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 267 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 268 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 269 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 270 48, 49, 50, 51, 52, 53, 54, 55,\ 271 56, 57, 58, 59, 60, 61, 62, 63} 272 #define CONFIG_SYS_NAND_ECCSIZE 256 273 #define CONFIG_SYS_NAND_ECCBYTES 3 274 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 275 #define CONFIG_SPL_NAND_SOFTECC 276 277 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 278 279 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 280 281 /* 282 * ethernet support 283 * 284 */ 285 #if defined(CONFIG_CMD_NET) 286 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 287 #define CONFIG_BOOTP_DNS2 288 #define CONFIG_BOOTP_SEND_HOSTNAME 289 #define CONFIG_NET_RETRY_COUNT 10 290 #endif 291 292 #define CONFIG_SPLASH_SCREEN 293 #define CONFIG_VIDEO_BMP_RLE8 294 295 #endif /* __CONFIG_H */ 296