1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 14 /* 15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 16 * for DDR ECC byte filling in the SPL before loading the main 17 * U-Boot into it. 18 */ 19 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 20 21 /* 22 * Commands configuration 23 */ 24 25 /* I2C */ 26 #define CONFIG_SYS_I2C 27 #define CONFIG_SYS_I2C_MVTWSI 28 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29 #define CONFIG_SYS_I2C_SLAVE 0x0 30 #define CONFIG_SYS_I2C_SPEED 100000 31 32 /* SPI NOR flash default params, used by sf commands */ 33 #define CONFIG_SF_DEFAULT_SPEED 1000000 34 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 35 36 /* Environment in SPI NOR flash */ 37 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 38 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 39 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 40 41 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 42 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 43 44 /* 45 * mv-common.h should be defined after CMD configs since it used them 46 * to enable certain macros 47 */ 48 #include "mv-common.h" 49 50 /* 51 * Memory layout while starting into the bin_hdr via the 52 * BootROM: 53 * 54 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 55 * 0x4000.4030 bin_hdr start address 56 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 57 * 0x4007.fffc BootROM stack top 58 * 59 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 60 * L2 cache thus cannot be used. 61 */ 62 63 /* SPL */ 64 /* Defines for SPL */ 65 #define CONFIG_SPL_TEXT_BASE 0x40004030 66 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 67 68 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 69 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MALLOC_SIMPLE 73 #endif 74 75 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 76 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 77 78 /* SPL related SPI defines */ 79 #define CONFIG_SPL_SPI_LOAD 80 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 81 82 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 83 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 84 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 85 86 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 87