xref: /openbmc/u-boot/include/configs/maxbcm.h (revision 3aa4b703)
1 /*
2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _CONFIG_DB_MV7846MP_GP_H
8 #define _CONFIG_DB_MV7846MP_GP_H
9 
10 /*
11  * High Level Configuration Options (easy to change)
12  */
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
14 
15 /*
16  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17  * for DDR ECC byte filling in the SPL before loading the main
18  * U-Boot into it.
19  */
20 #define	CONFIG_SYS_TEXT_BASE	0x00800000
21 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
22 
23 /*
24  * Commands configuration
25  */
26 
27 /* I2C */
28 #define CONFIG_SYS_I2C
29 #define CONFIG_SYS_I2C_MVTWSI
30 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
31 #define CONFIG_SYS_I2C_SLAVE		0x0
32 #define CONFIG_SYS_I2C_SPEED		100000
33 
34 /* SPI NOR flash default params, used by sf commands */
35 #define CONFIG_SF_DEFAULT_SPEED		1000000
36 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
37 
38 /* Environment in SPI NOR flash */
39 #define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
40 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
41 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
42 
43 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
44 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
45 
46 #define CONFIG_SYS_ALT_MEMTEST
47 
48 /*
49  * mv-common.h should be defined after CMD configs since it used them
50  * to enable certain macros
51  */
52 #include "mv-common.h"
53 
54 /*
55  * Memory layout while starting into the bin_hdr via the
56  * BootROM:
57  *
58  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
59  * 0x4000.4030			bin_hdr start address
60  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
61  * 0x4007.fffc			BootROM stack top
62  *
63  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
64  * L2 cache thus cannot be used.
65  */
66 
67 /* SPL */
68 /* Defines for SPL */
69 #define CONFIG_SPL_FRAMEWORK
70 #define CONFIG_SPL_TEXT_BASE		0x40004030
71 #define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
72 
73 #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
74 #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
75 
76 #ifdef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MALLOC_SIMPLE
78 #endif
79 
80 #define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
81 #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
82 
83 /* SPL related SPI defines */
84 #define CONFIG_SPL_SPI_LOAD
85 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
86 
87 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
88 #define CONFIG_DDR_FIXED_SIZE		(1 << 20)	/* 1GiB */
89 #define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
90 
91 #endif /* _CONFIG_DB_MV7846MP_GP_H */
92