1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef _CONFIG_DB_MV7846MP_GP_H 7 #define _CONFIG_DB_MV7846MP_GP_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 13 /* 14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 15 * for DDR ECC byte filling in the SPL before loading the main 16 * U-Boot into it. 17 */ 18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 19 20 /* 21 * Commands configuration 22 */ 23 24 /* I2C */ 25 #define CONFIG_SYS_I2C 26 #define CONFIG_SYS_I2C_MVTWSI 27 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 28 #define CONFIG_SYS_I2C_SLAVE 0x0 29 #define CONFIG_SYS_I2C_SPEED 100000 30 31 /* SPI NOR flash default params, used by sf commands */ 32 33 /* Environment in SPI NOR flash */ 34 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 35 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 36 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 37 38 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 39 40 /* 41 * mv-common.h should be defined after CMD configs since it used them 42 * to enable certain macros 43 */ 44 #include "mv-common.h" 45 46 /* 47 * Memory layout while starting into the bin_hdr via the 48 * BootROM: 49 * 50 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 51 * 0x4000.4030 bin_hdr start address 52 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 53 * 0x4007.fffc BootROM stack top 54 * 55 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 56 * L2 cache thus cannot be used. 57 */ 58 59 /* SPL */ 60 /* Defines for SPL */ 61 #define CONFIG_SPL_TEXT_BASE 0x40004030 62 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 63 64 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 65 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 66 67 #ifdef CONFIG_SPL_BUILD 68 #define CONFIG_SYS_MALLOC_SIMPLE 69 #endif 70 71 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 72 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 73 74 /* SPL related SPI defines */ 75 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 76 77 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 78 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 79 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 80 81 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 82