1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_RDB_H 8 #define __LS2_RDB_H 9 10 #include "ls2080a_common.h" 11 12 #ifdef CONFIG_FSL_QSPI 13 #ifdef CONFIG_TARGET_LS2081ARDB 14 #define CONFIG_QIXIS_I2C_ACCESS 15 #endif 16 #define CONFIG_SYS_I2C_EARLY_INIT 17 #endif 18 19 #define I2C_MUX_CH_VOL_MONITOR 0xa 20 #define I2C_VOL_MONITOR_ADDR 0x38 21 #define CONFIG_VOL_MONITOR_IR36021_READ 22 #define CONFIG_VOL_MONITOR_IR36021_SET 23 24 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 25 #ifndef CONFIG_SPL_BUILD 26 #define CONFIG_VID 27 #endif 28 /* step the IR regulator in 5mV increments */ 29 #define IR_VDD_STEP_DOWN 5 30 #define IR_VDD_STEP_UP 5 31 /* The lowest and highest voltage allowed for LS2080ARDB */ 32 #define VDD_MV_MIN 819 33 #define VDD_MV_MAX 1212 34 35 #ifndef __ASSEMBLY__ 36 unsigned long get_board_sys_clk(void); 37 #endif 38 39 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 40 #define CONFIG_DDR_CLK_FREQ 133333333 41 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 42 43 #define CONFIG_DDR_SPD 44 #define CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #define SPD_EEPROM_ADDRESS1 0x51 48 #define SPD_EEPROM_ADDRESS2 0x52 49 #define SPD_EEPROM_ADDRESS3 0x53 50 #define SPD_EEPROM_ADDRESS4 0x54 51 #define SPD_EEPROM_ADDRESS5 0x55 52 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 53 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 54 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 55 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 56 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 58 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 59 #endif 60 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 61 62 /* SATA */ 63 #define CONFIG_SCSI_AHCI_PLAT 64 65 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 66 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 67 68 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 69 #define CONFIG_SYS_SCSI_MAX_LUN 1 70 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 71 CONFIG_SYS_SCSI_MAX_LUN) 72 73 #ifndef CONFIG_FSL_QSPI 74 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 75 76 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 77 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 78 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 79 80 #define CONFIG_SYS_NOR0_CSPR \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 87 CSPR_PORT_SIZE_16 | \ 88 CSPR_MSEL_NOR | \ 89 CSPR_V) 90 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 91 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 92 FTIM0_NOR_TEADC(0x5) | \ 93 FTIM0_NOR_TEAHC(0x5)) 94 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 95 FTIM1_NOR_TRAD_NOR(0x1a) |\ 96 FTIM1_NOR_TSEQRAD_NOR(0x13)) 97 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 98 FTIM2_NOR_TCH(0x4) | \ 99 FTIM2_NOR_TWPH(0x0E) | \ 100 FTIM2_NOR_TWP(0x1c)) 101 #define CONFIG_SYS_NOR_FTIM3 0x04000000 102 #define CONFIG_SYS_IFC_CCR 0x01000000 103 104 #ifdef CONFIG_MTD_NOR_FLASH 105 #define CONFIG_SYS_FLASH_QUIET_TEST 106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 107 108 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 115 CONFIG_SYS_FLASH_BASE + 0x40000000} 116 #endif 117 118 #define CONFIG_NAND_FSL_IFC 119 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 120 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 121 122 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 123 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 124 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 125 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 126 | CSPR_V) 127 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 128 129 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 130 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 131 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 132 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 133 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 134 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 135 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 136 137 #define CONFIG_SYS_NAND_ONFI_DETECTION 138 139 /* ONFI NAND Flash mode0 Timing Params */ 140 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 141 FTIM0_NAND_TWP(0x30) | \ 142 FTIM0_NAND_TWCHT(0x0e) | \ 143 FTIM0_NAND_TWH(0x14)) 144 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 145 FTIM1_NAND_TWBE(0xab) | \ 146 FTIM1_NAND_TRR(0x1c) | \ 147 FTIM1_NAND_TRP(0x30)) 148 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 149 FTIM2_NAND_TREH(0x14) | \ 150 FTIM2_NAND_TWHRE(0x3c)) 151 #define CONFIG_SYS_NAND_FTIM3 0x0 152 153 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 154 #define CONFIG_SYS_MAX_NAND_DEVICE 1 155 #define CONFIG_MTD_NAND_VERIFY_WRITE 156 157 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 158 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 159 #define QIXIS_LBMAP_SWITCH 0x06 160 #define QIXIS_LBMAP_MASK 0x0f 161 #define QIXIS_LBMAP_SHIFT 0 162 #define QIXIS_LBMAP_DFLTBANK 0x00 163 #define QIXIS_LBMAP_ALTBANK 0x04 164 #define QIXIS_LBMAP_NAND 0x09 165 #define QIXIS_RST_CTL_RESET 0x31 166 #define QIXIS_RST_CTL_RESET_EN 0x30 167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 168 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 170 #define QIXIS_RCW_SRC_NAND 0x119 171 #define QIXIS_RST_FORCE_MEM 0x01 172 173 #define CONFIG_SYS_CSPR3_EXT (0x0) 174 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 175 | CSPR_PORT_SIZE_8 \ 176 | CSPR_MSEL_GPCM \ 177 | CSPR_V) 178 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 179 | CSPR_PORT_SIZE_8 \ 180 | CSPR_MSEL_GPCM \ 181 | CSPR_V) 182 183 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 184 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 185 /* QIXIS Timing parameters for IFC CS3 */ 186 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 187 FTIM0_GPCM_TEADC(0x0e) | \ 188 FTIM0_GPCM_TEAHC(0x0e)) 189 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 190 FTIM1_GPCM_TRAD(0x3f)) 191 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 192 FTIM2_GPCM_TCH(0xf) | \ 193 FTIM2_GPCM_TWP(0x3E)) 194 #define CONFIG_SYS_CS3_FTIM3 0x0 195 196 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 197 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 198 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 199 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 200 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 201 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 202 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 203 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 204 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 205 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 206 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 207 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 208 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 209 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 210 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 211 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 212 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 213 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 214 215 #define CONFIG_ENV_OFFSET (2048 * 1024) 216 #define CONFIG_ENV_SECT_SIZE 0x20000 217 #define CONFIG_ENV_SIZE 0x2000 218 #define CONFIG_SPL_PAD_TO 0x80000 219 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 220 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 221 #else 222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 224 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 225 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 226 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 227 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 228 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 229 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 230 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 231 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 232 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 233 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 234 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 235 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 236 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 237 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 238 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 239 240 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 241 #define CONFIG_ENV_SECT_SIZE 0x20000 242 #define CONFIG_ENV_SIZE 0x2000 243 #endif 244 245 /* Debug Server firmware */ 246 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 247 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 248 #endif 249 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 250 251 #ifdef CONFIG_TARGET_LS2081ARDB 252 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 253 #define QIXIS_QMAP_MASK 0x07 254 #define QIXIS_QMAP_SHIFT 5 255 #define QIXIS_LBMAP_DFLTBANK 0x00 256 #define QIXIS_LBMAP_QSPI 0x00 257 #define QIXIS_RCW_SRC_QSPI 0x62 258 #define QIXIS_LBMAP_ALTBANK 0x20 259 #define QIXIS_RST_CTL_RESET 0x31 260 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 261 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 262 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 263 #define QIXIS_LBMAP_MASK 0x0f 264 #define QIXIS_RST_CTL_RESET_EN 0x30 265 #endif 266 267 /* 268 * I2C 269 */ 270 #ifdef CONFIG_TARGET_LS2081ARDB 271 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 272 #endif 273 #define I2C_MUX_PCA_ADDR 0x75 274 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 275 276 /* I2C bus multiplexer */ 277 #define I2C_MUX_CH_DEFAULT 0x8 278 279 /* SPI */ 280 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 281 #ifdef CONFIG_FSL_DSPI 282 #define CONFIG_SPI_FLASH_STMICRO 283 #endif 284 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 285 #define FSL_QSPI_FLASH_NUM 2 286 #endif 287 288 /* 289 * RTC configuration 290 */ 291 #define RTC 292 #ifdef CONFIG_TARGET_LS2081ARDB 293 #define CONFIG_RTC_PCF8563 1 294 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 295 #else 296 #define CONFIG_RTC_DS3231 1 297 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 298 #endif 299 300 /* EEPROM */ 301 #define CONFIG_ID_EEPROM 302 #define CONFIG_SYS_I2C_EEPROM_NXID 303 #define CONFIG_SYS_EEPROM_BUS_NUM 0 304 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 305 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 306 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 307 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 308 309 #define CONFIG_FSL_MEMAC 310 311 #ifdef CONFIG_PCI 312 #define CONFIG_PCI_SCAN_SHOW 313 #endif 314 315 /* MMC */ 316 #ifdef CONFIG_MMC 317 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 318 #endif 319 320 #define BOOT_TARGET_DEVICES(func) \ 321 func(USB, usb, 0) \ 322 func(MMC, mmc, 0) \ 323 func(SCSI, scsi, 0) 324 #include <config_distro_bootcmd.h> 325 326 #ifdef CONFIG_QSPI_BOOT 327 #define MC_INIT_CMD \ 328 "mcinitcmd=env exists secureboot && " \ 329 "esbc_validate 0x20700000 && " \ 330 "esbc_validate 0x20740000;" \ 331 "fsl_mc start mc 0x20a00000 0x20e00000 \0" 332 #elif defined(CONFIG_SD_BOOT) 333 #define MC_INIT_CMD \ 334 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 335 "mmc read 0x80100000 0x7000 0x800;" \ 336 "env exists secureboot && " \ 337 "mmc read 0x80700000 0x3800 0x10 && " \ 338 "mmc read 0x80740000 0x3A00 0x10 && " \ 339 "esbc_validate 0x80700000 && " \ 340 "esbc_validate 0x80740000 ;" \ 341 "fsl_mc start mc 0x80000000 0x80100000\0" \ 342 "mcmemsize=0x70000000\0" 343 #else 344 #define MC_INIT_CMD \ 345 "mcinitcmd=env exists secureboot && " \ 346 "esbc_validate 0x580700000 && " \ 347 "esbc_validate 0x580740000; " \ 348 "fsl_mc start mc 0x580a00000 0x580e00000 \0" 349 #endif 350 351 /* Initial environment variables */ 352 #undef CONFIG_EXTRA_ENV_SETTINGS 353 #define CONFIG_EXTRA_ENV_SETTINGS \ 354 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 355 "ramdisk_addr=0x800000\0" \ 356 "ramdisk_size=0x2000000\0" \ 357 "fdt_high=0xa0000000\0" \ 358 "initrd_high=0xffffffffffffffff\0" \ 359 "fdt_addr=0x64f00000\0" \ 360 "kernel_addr=0x581000000\0" \ 361 "kernel_start=0x1000000\0" \ 362 "kernelheader_start=0x800000\0" \ 363 "scriptaddr=0x80000000\0" \ 364 "scripthdraddr=0x80080000\0" \ 365 "fdtheader_addr_r=0x80100000\0" \ 366 "kernelheader_addr_r=0x80200000\0" \ 367 "kernelheader_addr=0x580800000\0" \ 368 "kernel_addr_r=0x81000000\0" \ 369 "kernelheader_size=0x40000\0" \ 370 "fdt_addr_r=0x90000000\0" \ 371 "load_addr=0xa0000000\0" \ 372 "kernel_size=0x2800000\0" \ 373 "kernel_addr_sd=0x8000\0" \ 374 "kernel_size_sd=0x14000\0" \ 375 "console=ttyAMA0,38400n8\0" \ 376 "mcmemsize=0x70000000\0" \ 377 "sd_bootcmd=echo Trying load from SD ..;" \ 378 "mmcinfo; mmc read $load_addr " \ 379 "$kernel_addr_sd $kernel_size_sd && " \ 380 "bootm $load_addr#$board\0" \ 381 MC_INIT_CMD \ 382 BOOTENV \ 383 "boot_scripts=ls2088ardb_boot.scr\0" \ 384 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ 385 "scan_dev_for_boot_part=" \ 386 "part list ${devtype} ${devnum} devplist; " \ 387 "env exists devplist || setenv devplist 1; " \ 388 "for distro_bootpart in ${devplist}; do " \ 389 "if fstype ${devtype} " \ 390 "${devnum}:${distro_bootpart} " \ 391 "bootfstype; then " \ 392 "run scan_dev_for_boot; " \ 393 "fi; " \ 394 "done\0" \ 395 "scan_dev_for_boot=" \ 396 "echo Scanning ${devtype} " \ 397 "${devnum}:${distro_bootpart}...; " \ 398 "for prefix in ${boot_prefixes}; do " \ 399 "run scan_dev_for_scripts; " \ 400 "done;\0" \ 401 "boot_a_script=" \ 402 "load ${devtype} ${devnum}:${distro_bootpart} " \ 403 "${scriptaddr} ${prefix}${script}; " \ 404 "env exists secureboot && load ${devtype} " \ 405 "${devnum}:${distro_bootpart} " \ 406 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 407 "&& esbc_validate ${scripthdraddr};" \ 408 "source ${scriptaddr}\0" \ 409 "qspi_bootcmd=echo Trying load from qspi..;" \ 410 "sf probe && sf read $load_addr " \ 411 "$kernel_start $kernel_size ; env exists secureboot &&" \ 412 "sf read $kernelheader_addr_r $kernelheader_start " \ 413 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 414 " bootm $load_addr#$board\0" \ 415 "nor_bootcmd=echo Trying load from nor..;" \ 416 "cp.b $kernel_addr $load_addr " \ 417 "$kernel_size ; env exists secureboot && " \ 418 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 419 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 420 "bootm $load_addr#$board\0" 421 422 #undef CONFIG_BOOTCOMMAND 423 #ifdef CONFIG_QSPI_BOOT 424 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 425 #define CONFIG_BOOTCOMMAND \ 426 "env exists mcinitcmd && env exists secureboot "\ 427 "&& esbc_validate 0x20780000; " \ 428 "env exists mcinitcmd && " \ 429 "fsl_mc lazyapply dpl 0x20d00000; " \ 430 "run distro_bootcmd;run qspi_bootcmd; " \ 431 "env exists secureboot && esbc_halt;" 432 #elif defined(CONFIG_SD_BOOT) 433 /* Try to boot an on-SD kernel first, then do normal distro boot */ 434 #define CONFIG_BOOTCOMMAND \ 435 "env exists mcinitcmd && env exists secureboot "\ 436 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ 437 "&& esbc_validate $load_addr; " \ 438 "env exists mcinitcmd && run mcinitcmd " \ 439 "&& mmc read 0x88000000 0x6800 0x800 " \ 440 "&& fsl_mc lazyapply dpl 0x88000000; " \ 441 "run distro_bootcmd;run sd_bootcmd; " \ 442 "env exists secureboot && esbc_halt;" 443 #else 444 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 445 #define CONFIG_BOOTCOMMAND \ 446 "env exists mcinitcmd && env exists secureboot "\ 447 "&& esbc_validate 0x580780000; env exists mcinitcmd "\ 448 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 449 "run distro_bootcmd;run nor_bootcmd; " \ 450 "env exists secureboot && esbc_halt;" 451 #endif 452 453 /* MAC/PHY configuration */ 454 #ifdef CONFIG_FSL_MC_ENET 455 #define CONFIG_PHY_CORTINA 456 #define CONFIG_SYS_CORTINA_FW_IN_NOR 457 #ifdef CONFIG_QSPI_BOOT 458 #define CONFIG_CORTINA_FW_ADDR 0x20980000 459 #else 460 #define CONFIG_CORTINA_FW_ADDR 0x580980000 461 #endif 462 #define CONFIG_CORTINA_FW_LENGTH 0x40000 463 464 #define CORTINA_PHY_ADDR1 0x10 465 #define CORTINA_PHY_ADDR2 0x11 466 #define CORTINA_PHY_ADDR3 0x12 467 #define CORTINA_PHY_ADDR4 0x13 468 #define AQ_PHY_ADDR1 0x00 469 #define AQ_PHY_ADDR2 0x01 470 #define AQ_PHY_ADDR3 0x02 471 #define AQ_PHY_ADDR4 0x03 472 #define AQR405_IRQ_MASK 0x36 473 474 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 475 #endif 476 477 #include <asm/fsl_secure_boot.h> 478 479 #endif /* __LS2_RDB_H */ 480