1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_RDB_H 9 #define __LS2_RDB_H 10 11 #include "ls2080a_common.h" 12 13 #undef CONFIG_CONS_INDEX 14 #define CONFIG_CONS_INDEX 2 15 16 #ifdef CONFIG_FSL_QSPI 17 #ifdef CONFIG_TARGET_LS2081ARDB 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #endif 20 #define CONFIG_SYS_I2C_EARLY_INIT 21 #define CONFIG_DISPLAY_BOARDINFO_LATE 22 #endif 23 24 #define I2C_MUX_CH_VOL_MONITOR 0xa 25 #define I2C_VOL_MONITOR_ADDR 0x38 26 #define CONFIG_VOL_MONITOR_IR36021_READ 27 #define CONFIG_VOL_MONITOR_IR36021_SET 28 29 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 30 #ifndef CONFIG_SPL_BUILD 31 #define CONFIG_VID 32 #endif 33 /* step the IR regulator in 5mV increments */ 34 #define IR_VDD_STEP_DOWN 5 35 #define IR_VDD_STEP_UP 5 36 /* The lowest and highest voltage allowed for LS2080ARDB */ 37 #define VDD_MV_MIN 819 38 #define VDD_MV_MAX 1212 39 40 #ifndef __ASSEMBLY__ 41 unsigned long get_board_sys_clk(void); 42 #endif 43 44 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 45 #define CONFIG_DDR_CLK_FREQ 133333333 46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 47 48 #define CONFIG_DDR_SPD 49 #define CONFIG_DDR_ECC 50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 52 #define SPD_EEPROM_ADDRESS1 0x51 53 #define SPD_EEPROM_ADDRESS2 0x52 54 #define SPD_EEPROM_ADDRESS3 0x53 55 #define SPD_EEPROM_ADDRESS4 0x54 56 #define SPD_EEPROM_ADDRESS5 0x55 57 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 58 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 59 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 60 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 61 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 62 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 63 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 64 #endif 65 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 66 67 /* SATA */ 68 #define CONFIG_LIBATA 69 #define CONFIG_SCSI_AHCI 70 #define CONFIG_SCSI_AHCI_PLAT 71 72 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 73 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 74 75 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 76 #define CONFIG_SYS_SCSI_MAX_LUN 1 77 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 78 CONFIG_SYS_SCSI_MAX_LUN) 79 80 #ifndef CONFIG_FSL_QSPI 81 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 82 83 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 84 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 85 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 86 87 #define CONFIG_SYS_NOR0_CSPR \ 88 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 89 CSPR_PORT_SIZE_16 | \ 90 CSPR_MSEL_NOR | \ 91 CSPR_V) 92 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 93 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 94 CSPR_PORT_SIZE_16 | \ 95 CSPR_MSEL_NOR | \ 96 CSPR_V) 97 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 98 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 99 FTIM0_NOR_TEADC(0x5) | \ 100 FTIM0_NOR_TEAHC(0x5)) 101 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 102 FTIM1_NOR_TRAD_NOR(0x1a) |\ 103 FTIM1_NOR_TSEQRAD_NOR(0x13)) 104 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 105 FTIM2_NOR_TCH(0x4) | \ 106 FTIM2_NOR_TWPH(0x0E) | \ 107 FTIM2_NOR_TWP(0x1c)) 108 #define CONFIG_SYS_NOR_FTIM3 0x04000000 109 #define CONFIG_SYS_IFC_CCR 0x01000000 110 111 #ifdef CONFIG_MTD_NOR_FLASH 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 115 #define CONFIG_SYS_FLASH_QUIET_TEST 116 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 117 118 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 119 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_FLASH_EMPTY_INFO 124 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 125 CONFIG_SYS_FLASH_BASE + 0x40000000} 126 #endif 127 128 #define CONFIG_NAND_FSL_IFC 129 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 130 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 131 132 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 133 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 134 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 135 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 136 | CSPR_V) 137 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 138 139 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 140 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 141 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 142 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 143 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 144 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 145 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 146 147 #define CONFIG_SYS_NAND_ONFI_DETECTION 148 149 /* ONFI NAND Flash mode0 Timing Params */ 150 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 151 FTIM0_NAND_TWP(0x30) | \ 152 FTIM0_NAND_TWCHT(0x0e) | \ 153 FTIM0_NAND_TWH(0x14)) 154 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 155 FTIM1_NAND_TWBE(0xab) | \ 156 FTIM1_NAND_TRR(0x1c) | \ 157 FTIM1_NAND_TRP(0x30)) 158 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 159 FTIM2_NAND_TREH(0x14) | \ 160 FTIM2_NAND_TWHRE(0x3c)) 161 #define CONFIG_SYS_NAND_FTIM3 0x0 162 163 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 164 #define CONFIG_SYS_MAX_NAND_DEVICE 1 165 #define CONFIG_MTD_NAND_VERIFY_WRITE 166 167 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 168 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 169 #define QIXIS_LBMAP_SWITCH 0x06 170 #define QIXIS_LBMAP_MASK 0x0f 171 #define QIXIS_LBMAP_SHIFT 0 172 #define QIXIS_LBMAP_DFLTBANK 0x00 173 #define QIXIS_LBMAP_ALTBANK 0x04 174 #define QIXIS_LBMAP_NAND 0x09 175 #define QIXIS_RST_CTL_RESET 0x31 176 #define QIXIS_RST_CTL_RESET_EN 0x30 177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 180 #define QIXIS_RCW_SRC_NAND 0x119 181 #define QIXIS_RST_FORCE_MEM 0x01 182 183 #define CONFIG_SYS_CSPR3_EXT (0x0) 184 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 185 | CSPR_PORT_SIZE_8 \ 186 | CSPR_MSEL_GPCM \ 187 | CSPR_V) 188 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 189 | CSPR_PORT_SIZE_8 \ 190 | CSPR_MSEL_GPCM \ 191 | CSPR_V) 192 193 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 194 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 195 /* QIXIS Timing parameters for IFC CS3 */ 196 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 197 FTIM0_GPCM_TEADC(0x0e) | \ 198 FTIM0_GPCM_TEAHC(0x0e)) 199 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 200 FTIM1_GPCM_TRAD(0x3f)) 201 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 202 FTIM2_GPCM_TCH(0xf) | \ 203 FTIM2_GPCM_TWP(0x3E)) 204 #define CONFIG_SYS_CS3_FTIM3 0x0 205 206 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 207 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 208 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 209 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 210 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 211 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 212 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 213 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 214 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 215 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 216 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 224 225 #define CONFIG_ENV_OFFSET (2048 * 1024) 226 #define CONFIG_ENV_SECT_SIZE 0x20000 227 #define CONFIG_ENV_SIZE 0x2000 228 #define CONFIG_SPL_PAD_TO 0x80000 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 230 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 231 #else 232 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 233 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 234 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 241 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 242 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 243 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 244 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 245 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 246 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 247 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 248 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 249 250 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 251 #define CONFIG_ENV_SECT_SIZE 0x20000 252 #define CONFIG_ENV_SIZE 0x2000 253 #endif 254 255 /* Debug Server firmware */ 256 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 257 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 258 #endif 259 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 260 261 #ifdef CONFIG_TARGET_LS2081ARDB 262 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 263 #define QIXIS_QMAP_MASK 0x07 264 #define QIXIS_QMAP_SHIFT 5 265 #define QIXIS_LBMAP_DFLTBANK 0x00 266 #define QIXIS_LBMAP_QSPI 0x00 267 #define QIXIS_RCW_SRC_QSPI 0x62 268 #define QIXIS_LBMAP_ALTBANK 0x20 269 #define QIXIS_RST_CTL_RESET 0x31 270 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 271 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 272 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 273 #define QIXIS_LBMAP_MASK 0x0f 274 #define QIXIS_RST_CTL_RESET_EN 0x30 275 #endif 276 277 /* 278 * I2C 279 */ 280 #ifdef CONFIG_TARGET_LS2081ARDB 281 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 282 #endif 283 #define I2C_MUX_PCA_ADDR 0x75 284 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 285 286 /* I2C bus multiplexer */ 287 #define I2C_MUX_CH_DEFAULT 0x8 288 289 /* SPI */ 290 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 291 #define CONFIG_SPI_FLASH 292 #ifdef CONFIG_FSL_QSPI 293 #define CONFIG_SPI_FLASH_STMICRO 294 #endif 295 #ifdef CONFIG_FSL_QSPI 296 #ifdef CONFIG_TARGET_LS2081ARDB 297 #define CONFIG_SPI_FLASH_STMICRO 298 #else 299 #define CONFIG_SPI_FLASH_SPANSION 300 #endif 301 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 302 #define FSL_QSPI_FLASH_NUM 2 303 #endif 304 #endif 305 306 /* 307 * RTC configuration 308 */ 309 #define RTC 310 #ifdef CONFIG_TARGET_LS2081ARDB 311 #define CONFIG_RTC_PCF8563 1 312 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 313 #else 314 #define CONFIG_RTC_DS3231 1 315 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 316 #endif 317 318 /* EEPROM */ 319 #define CONFIG_ID_EEPROM 320 #define CONFIG_SYS_I2C_EEPROM_NXID 321 #define CONFIG_SYS_EEPROM_BUS_NUM 0 322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 326 327 #define CONFIG_FSL_MEMAC 328 329 #ifdef CONFIG_PCI 330 #define CONFIG_PCI_SCAN_SHOW 331 #endif 332 333 /* MMC */ 334 #ifdef CONFIG_MMC 335 #define CONFIG_FSL_ESDHC 336 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 337 #endif 338 339 #define CONFIG_MISC_INIT_R 340 341 /* 342 * USB 343 */ 344 #define CONFIG_HAS_FSL_XHCI_USB 345 #define CONFIG_USB_XHCI_FSL 346 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 347 348 #undef CONFIG_CMDLINE_EDITING 349 #include <config_distro_defaults.h> 350 351 #define BOOT_TARGET_DEVICES(func) \ 352 func(USB, usb, 0) \ 353 func(MMC, mmc, 0) \ 354 func(SCSI, scsi, 0) \ 355 func(DHCP, dhcp, na) 356 #include <config_distro_bootcmd.h> 357 358 #ifdef CONFIG_QSPI_BOOT 359 #define MC_INIT_CMD \ 360 "mcinitcmd=env exists secureboot && " \ 361 "esbc_validate 0x20700000 && " \ 362 "esbc_validate 0x20740000;" \ 363 "fsl_mc start mc 0x20a00000 0x20e00000 \0" 364 #else 365 #define MC_INIT_CMD \ 366 "mcinitcmd=env exists secureboot && " \ 367 "esbc_validate 0x580700000 && " \ 368 "esbc_validate 0x580740000; " \ 369 "fsl_mc start mc 0x580a00000 0x580e00000 \0" 370 #endif 371 372 /* Initial environment variables */ 373 #undef CONFIG_EXTRA_ENV_SETTINGS 374 #define CONFIG_EXTRA_ENV_SETTINGS \ 375 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 376 "ramdisk_addr=0x800000\0" \ 377 "ramdisk_size=0x2000000\0" \ 378 "fdt_high=0xa0000000\0" \ 379 "initrd_high=0xffffffffffffffff\0" \ 380 "fdt_addr=0x64f00000\0" \ 381 "kernel_addr=0x65000000\0" \ 382 "kernel_start=0x1000000\0" \ 383 "kernelheader_start=0x800000\0" \ 384 "scriptaddr=0x80000000\0" \ 385 "scripthdraddr=0x80080000\0" \ 386 "fdtheader_addr_r=0x80100000\0" \ 387 "kernelheader_addr_r=0x80200000\0" \ 388 "kernelheader_addr=0x580800000\0" \ 389 "kernel_addr_r=0x81000000\0" \ 390 "kernelheader_size=0x40000\0" \ 391 "fdt_addr_r=0x90000000\0" \ 392 "load_addr=0xa0000000\0" \ 393 "kernel_size=0x2800000\0" \ 394 "console=ttyAMA0,38400n8\0" \ 395 MC_INIT_CMD \ 396 BOOTENV \ 397 "boot_scripts=ls2088ardb_boot.scr\0" \ 398 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ 399 "scan_dev_for_boot_part=" \ 400 "part list ${devtype} ${devnum} devplist; " \ 401 "env exists devplist || setenv devplist 1; " \ 402 "for distro_bootpart in ${devplist}; do " \ 403 "if fstype ${devtype} " \ 404 "${devnum}:${distro_bootpart} " \ 405 "bootfstype; then " \ 406 "run scan_dev_for_boot; " \ 407 "fi; " \ 408 "done\0" \ 409 "scan_dev_for_boot=" \ 410 "echo Scanning ${devtype} " \ 411 "${devnum}:${distro_bootpart}...; " \ 412 "for prefix in ${boot_prefixes}; do " \ 413 "run scan_dev_for_scripts; " \ 414 "done;\0" \ 415 "boot_a_script=" \ 416 "load ${devtype} ${devnum}:${distro_bootpart} " \ 417 "${scriptaddr} ${prefix}${script}; " \ 418 "env exists secureboot && load ${devtype} " \ 419 "${devnum}:${distro_bootpart} " \ 420 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 421 "&& esbc_validate ${scripthdraddr};" \ 422 "source ${scriptaddr}\0" \ 423 "installer=load mmc 0:2 $load_addr " \ 424 "/flex_installer_arm64.itb; " \ 425 "bootm $load_addr#ls2088ardb\0" \ 426 "qspi_bootcmd=echo Trying load from qspi..;" \ 427 "sf probe && sf read $load_addr " \ 428 "$kernel_start $kernel_size ; env exists secureboot &&" \ 429 "sf read $kernelheader_addr_r $kernelheader_start " \ 430 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 431 " bootm $load_addr#$board\0" \ 432 "nor_bootcmd=echo Trying load from nor..;" \ 433 "cp.b $kernel_addr $load_addr " \ 434 "$kernel_size ; env exists secureboot && " \ 435 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 436 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 437 "bootm $load_addr#$board\0" 438 439 #undef CONFIG_BOOTCOMMAND 440 #ifdef CONFIG_QSPI_BOOT 441 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 442 #define CONFIG_BOOTCOMMAND \ 443 "env exists mcinitcmd && env exists secureboot "\ 444 "&& esbc_validate 0x20780000; " \ 445 "env exists mcinitcmd && " \ 446 "fsl_mc lazyapply dpl 0x20d00000; " \ 447 "run distro_bootcmd;run qspi_bootcmd; " \ 448 "env exists secureboot && esbc_halt; " 449 #else 450 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 451 #define CONFIG_BOOTCOMMAND \ 452 "env exists mcinitcmd && env exists secureboot "\ 453 "&& esbc_validate 0x580780000; env exists mcinitcmd "\ 454 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 455 "run distro_bootcmd;run nor_bootcmd; " \ 456 "env exists secureboot && esbc_halt; " 457 #endif 458 459 /* MAC/PHY configuration */ 460 #ifdef CONFIG_FSL_MC_ENET 461 #define CONFIG_PHYLIB_10G 462 #define CONFIG_PHY_AQUANTIA 463 #define CONFIG_PHY_CORTINA 464 #define CONFIG_SYS_CORTINA_FW_IN_NOR 465 #ifdef CONFIG_QSPI_BOOT 466 #define CONFIG_CORTINA_FW_ADDR 0x20980000 467 #else 468 #define CONFIG_CORTINA_FW_ADDR 0x580980000 469 #endif 470 #define CONFIG_CORTINA_FW_LENGTH 0x40000 471 472 #define CORTINA_PHY_ADDR1 0x10 473 #define CORTINA_PHY_ADDR2 0x11 474 #define CORTINA_PHY_ADDR3 0x12 475 #define CORTINA_PHY_ADDR4 0x13 476 #define AQ_PHY_ADDR1 0x00 477 #define AQ_PHY_ADDR2 0x01 478 #define AQ_PHY_ADDR3 0x02 479 #define AQ_PHY_ADDR4 0x03 480 #define AQR405_IRQ_MASK 0x36 481 482 #define CONFIG_MII 483 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 484 #define CONFIG_PHY_AQUANTIA 485 #endif 486 487 #include <asm/fsl_secure_boot.h> 488 489 #endif /* __LS2_RDB_H */ 490