xref: /openbmc/u-boot/include/configs/ls2080ardb.h (revision 6183b295)
1 /*
2  * Copyright 2017 NXP
3  * Copyright 2015 Freescale Semiconductor
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __LS2_RDB_H
9 #define __LS2_RDB_H
10 
11 #include "ls2080a_common.h"
12 
13 #undef CONFIG_CONS_INDEX
14 #define CONFIG_CONS_INDEX       2
15 
16 #ifdef CONFIG_FSL_QSPI
17 #ifdef CONFIG_TARGET_LS2081ARDB
18 #define CONFIG_QIXIS_I2C_ACCESS
19 #endif
20 #define CONFIG_SYS_I2C_EARLY_INIT
21 #define CONFIG_DISPLAY_BOARDINFO_LATE
22 #endif
23 
24 #define I2C_MUX_CH_VOL_MONITOR		0xa
25 #define I2C_VOL_MONITOR_ADDR		0x38
26 #define CONFIG_VOL_MONITOR_IR36021_READ
27 #define CONFIG_VOL_MONITOR_IR36021_SET
28 
29 #define CONFIG_VID_FLS_ENV		"ls2080ardb_vdd_mv"
30 #ifndef CONFIG_SPL_BUILD
31 #define CONFIG_VID
32 #endif
33 /* step the IR regulator in 5mV increments */
34 #define IR_VDD_STEP_DOWN		5
35 #define IR_VDD_STEP_UP			5
36 /* The lowest and highest voltage allowed for LS2080ARDB */
37 #define VDD_MV_MIN			819
38 #define VDD_MV_MAX			1212
39 
40 #ifndef __ASSEMBLY__
41 unsigned long get_board_sys_clk(void);
42 #endif
43 
44 #define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
45 #define CONFIG_DDR_CLK_FREQ		133333333
46 #define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
47 
48 #define CONFIG_DDR_SPD
49 #define CONFIG_DDR_ECC
50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
51 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
52 #define SPD_EEPROM_ADDRESS1	0x51
53 #define SPD_EEPROM_ADDRESS2	0x52
54 #define SPD_EEPROM_ADDRESS3	0x53
55 #define SPD_EEPROM_ADDRESS4	0x54
56 #define SPD_EEPROM_ADDRESS5	0x55
57 #define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
58 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
59 #define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
60 #define CONFIG_DIMM_SLOTS_PER_CTLR		2
61 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
62 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
63 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
64 #endif
65 #define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
66 
67 /* SATA */
68 #define CONFIG_LIBATA
69 #define CONFIG_SCSI_AHCI
70 #define CONFIG_SCSI_AHCI_PLAT
71 #define CONFIG_SCSI
72 
73 #define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
74 #define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2
75 
76 #define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
77 #define CONFIG_SYS_SCSI_MAX_LUN			1
78 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
79 						CONFIG_SYS_SCSI_MAX_LUN)
80 
81 #ifndef CONFIG_FSL_QSPI
82 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
83 
84 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
85 #define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
86 #define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
87 
88 #define CONFIG_SYS_NOR0_CSPR					\
89 	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
90 	CSPR_PORT_SIZE_16					| \
91 	CSPR_MSEL_NOR						| \
92 	CSPR_V)
93 #define CONFIG_SYS_NOR0_CSPR_EARLY				\
94 	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
95 	CSPR_PORT_SIZE_16					| \
96 	CSPR_MSEL_NOR						| \
97 	CSPR_V)
98 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
99 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
100 				FTIM0_NOR_TEADC(0x5) | \
101 				FTIM0_NOR_TEAHC(0x5))
102 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
103 				FTIM1_NOR_TRAD_NOR(0x1a) |\
104 				FTIM1_NOR_TSEQRAD_NOR(0x13))
105 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
106 				FTIM2_NOR_TCH(0x4) | \
107 				FTIM2_NOR_TWPH(0x0E) | \
108 				FTIM2_NOR_TWP(0x1c))
109 #define CONFIG_SYS_NOR_FTIM3	0x04000000
110 #define CONFIG_SYS_IFC_CCR	0x01000000
111 
112 #ifdef CONFIG_MTD_NOR_FLASH
113 #define CONFIG_FLASH_CFI_DRIVER
114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #define CONFIG_SYS_FLASH_QUIET_TEST
117 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
118 
119 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
120 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
121 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
122 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
123 
124 #define CONFIG_SYS_FLASH_EMPTY_INFO
125 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
126 					 CONFIG_SYS_FLASH_BASE + 0x40000000}
127 #endif
128 
129 #define CONFIG_NAND_FSL_IFC
130 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
131 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
132 
133 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
134 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
135 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
136 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
137 				| CSPR_V)
138 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
139 
140 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
141 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
142 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
143 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
144 				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
145 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
146 				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
147 
148 #define CONFIG_SYS_NAND_ONFI_DETECTION
149 
150 /* ONFI NAND Flash mode0 Timing Params */
151 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
152 					FTIM0_NAND_TWP(0x30)   | \
153 					FTIM0_NAND_TWCHT(0x0e) | \
154 					FTIM0_NAND_TWH(0x14))
155 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
156 					FTIM1_NAND_TWBE(0xab)  | \
157 					FTIM1_NAND_TRR(0x1c)   | \
158 					FTIM1_NAND_TRP(0x30))
159 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
160 					FTIM2_NAND_TREH(0x14) | \
161 					FTIM2_NAND_TWHRE(0x3c))
162 #define CONFIG_SYS_NAND_FTIM3		0x0
163 
164 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
165 #define CONFIG_SYS_MAX_NAND_DEVICE	1
166 #define CONFIG_MTD_NAND_VERIFY_WRITE
167 #define CONFIG_CMD_NAND
168 
169 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
170 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
171 #define QIXIS_LBMAP_SWITCH		0x06
172 #define QIXIS_LBMAP_MASK		0x0f
173 #define QIXIS_LBMAP_SHIFT		0
174 #define QIXIS_LBMAP_DFLTBANK		0x00
175 #define QIXIS_LBMAP_ALTBANK		0x04
176 #define QIXIS_LBMAP_NAND		0x09
177 #define QIXIS_RST_CTL_RESET		0x31
178 #define QIXIS_RST_CTL_RESET_EN		0x30
179 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
180 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
181 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
182 #define QIXIS_RCW_SRC_NAND		0x119
183 #define	QIXIS_RST_FORCE_MEM		0x01
184 
185 #define CONFIG_SYS_CSPR3_EXT	(0x0)
186 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
187 				| CSPR_PORT_SIZE_8 \
188 				| CSPR_MSEL_GPCM \
189 				| CSPR_V)
190 #define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
191 				| CSPR_PORT_SIZE_8 \
192 				| CSPR_MSEL_GPCM \
193 				| CSPR_V)
194 
195 #define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
196 #define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
197 /* QIXIS Timing parameters for IFC CS3 */
198 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
199 					FTIM0_GPCM_TEADC(0x0e) | \
200 					FTIM0_GPCM_TEAHC(0x0e))
201 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
202 					FTIM1_GPCM_TRAD(0x3f))
203 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
204 					FTIM2_GPCM_TCH(0xf) | \
205 					FTIM2_GPCM_TWP(0x3E))
206 #define CONFIG_SYS_CS3_FTIM3		0x0
207 
208 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
209 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
210 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
211 #define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
212 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
213 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
214 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
215 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
216 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
217 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
218 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
219 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
220 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
221 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
222 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
223 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
224 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
225 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
226 
227 #define CONFIG_ENV_IS_IN_NAND
228 #define CONFIG_ENV_OFFSET		(2048 * 1024)
229 #define CONFIG_ENV_SECT_SIZE		0x20000
230 #define CONFIG_ENV_SIZE			0x2000
231 #define CONFIG_SPL_PAD_TO		0x80000
232 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
233 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
234 #else
235 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
236 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
237 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
238 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
239 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
240 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
241 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
242 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
243 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
245 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
249 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
250 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
251 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
252 
253 #define CONFIG_ENV_IS_IN_FLASH
254 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
255 #define CONFIG_ENV_SECT_SIZE		0x20000
256 #define CONFIG_ENV_SIZE			0x2000
257 #endif
258 
259 /* Debug Server firmware */
260 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
261 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
262 #endif
263 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
264 
265 #ifdef CONFIG_TARGET_LS2081ARDB
266 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
267 #define QIXIS_QMAP_MASK			0x07
268 #define QIXIS_QMAP_SHIFT		5
269 #define QIXIS_LBMAP_DFLTBANK		0x00
270 #define QIXIS_LBMAP_QSPI		0x00
271 #define QIXIS_RCW_SRC_QSPI		0x62
272 #define QIXIS_LBMAP_ALTBANK		0x20
273 #define QIXIS_RST_CTL_RESET		0x31
274 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
275 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
276 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
277 #define QIXIS_LBMAP_MASK		0x0f
278 #define QIXIS_RST_CTL_RESET_EN		0x30
279 #endif
280 
281 /*
282  * I2C
283  */
284 #ifdef CONFIG_TARGET_LS2081ARDB
285 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
286 #endif
287 #define I2C_MUX_PCA_ADDR		0x75
288 #define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
289 
290 /* I2C bus multiplexer */
291 #define I2C_MUX_CH_DEFAULT      0x8
292 
293 /* SPI */
294 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
295 #define CONFIG_SPI_FLASH
296 #ifdef CONFIG_FSL_QSPI
297 #define CONFIG_SPI_FLASH_STMICRO
298 #endif
299 #ifdef CONFIG_FSL_QSPI
300 #ifdef CONFIG_TARGET_LS2081ARDB
301 #define CONFIG_SPI_FLASH_STMICRO
302 #else
303 #define CONFIG_SPI_FLASH_SPANSION
304 #endif
305 #define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
306 #define FSL_QSPI_FLASH_NUM		2
307 #endif
308 #endif
309 
310 /*
311  * RTC configuration
312  */
313 #define RTC
314 #ifdef CONFIG_TARGET_LS2081ARDB
315 #define CONFIG_RTC_PCF8563		1
316 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
317 #else
318 #define CONFIG_RTC_DS3231               1
319 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
320 #endif
321 
322 /* EEPROM */
323 #define CONFIG_ID_EEPROM
324 #define CONFIG_SYS_I2C_EEPROM_NXID
325 #define CONFIG_SYS_EEPROM_BUS_NUM	0
326 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
330 
331 #define CONFIG_FSL_MEMAC
332 
333 #ifdef CONFIG_PCI
334 #define CONFIG_PCI_SCAN_SHOW
335 #define CONFIG_CMD_PCI
336 #endif
337 
338 /*  MMC  */
339 #ifdef CONFIG_MMC
340 #define CONFIG_FSL_ESDHC
341 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
342 #endif
343 
344 #define CONFIG_MISC_INIT_R
345 
346 /*
347  * USB
348  */
349 #define CONFIG_HAS_FSL_XHCI_USB
350 #define CONFIG_USB_XHCI_FSL
351 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
352 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
353 
354 #undef CONFIG_CMDLINE_EDITING
355 #include <config_distro_defaults.h>
356 
357 #define BOOT_TARGET_DEVICES(func) \
358 	func(USB, usb, 0) \
359 	func(MMC, mmc, 0) \
360 	func(SCSI, scsi, 0) \
361 	func(DHCP, dhcp, na)
362 #include <config_distro_bootcmd.h>
363 
364 /* Initial environment variables */
365 #undef CONFIG_EXTRA_ENV_SETTINGS
366 #ifdef CONFIG_SECURE_BOOT
367 #define CONFIG_EXTRA_ENV_SETTINGS		\
368 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
369 	"scriptaddr=0x80800000\0"		\
370 	"kernel_addr_r=0x81000000\0"		\
371 	"pxefile_addr_r=0x81000000\0"		\
372 	"fdt_addr_r=0x88000000\0"		\
373 	"ramdisk_addr_r=0x89000000\0"		\
374 	"loadaddr=0x80100000\0"			\
375 	"kernel_addr=0x100000\0"		\
376 	"ramdisk_addr=0x800000\0"		\
377 	"ramdisk_size=0x2000000\0"		\
378 	"fdt_high=0xa0000000\0"			\
379 	"initrd_high=0xffffffffffffffff\0"	\
380 	"kernel_start=0x581000000\0"		\
381 	"kernel_load=0xa0000000\0"		\
382 	"kernel_size=0x2800000\0"		\
383 	"mcmemsize=0x40000000\0"		\
384 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
385 	"mcinitcmd=esbc_validate 0x580700000;"  \
386 	"esbc_validate 0x580740000;"            \
387 	"fsl_mc start mc 0x580a00000"           \
388 	" 0x580e00000 \0"                       \
389 	BOOTENV
390 #else
391 #ifdef CONFIG_QSPI_BOOT
392 #define CONFIG_EXTRA_ENV_SETTINGS		\
393 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
394 	"scriptaddr=0x80800000\0"		\
395 	"kernel_addr_r=0x81000000\0"		\
396 	"pxefile_addr_r=0x81000000\0"		\
397 	"fdt_addr_r=0x88000000\0"		\
398 	"ramdisk_addr_r=0x89000000\0"		\
399 	"loadaddr=0x80100000\0"			\
400 	"kernel_addr=0x100000\0"		\
401 	"ramdisk_size=0x2000000\0"		\
402 	"fdt_high=0xa0000000\0"			\
403 	"initrd_high=0xffffffffffffffff\0"	\
404 	"kernel_start=0x21000000\0"		\
405 	"mcmemsize=0x40000000\0"		\
406 	"mcinitcmd=fsl_mc start mc 0x20a00000" \
407 	" 0x20e00000 \0"                       \
408 	BOOTENV
409 #else
410 #define CONFIG_EXTRA_ENV_SETTINGS		\
411 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
412 	"scriptaddr=0x80800000\0"		\
413 	"kernel_addr_r=0x81000000\0"		\
414 	"pxefile_addr_r=0x81000000\0"		\
415 	"fdt_addr_r=0x88000000\0"		\
416 	"ramdisk_addr_r=0x89000000\0"		\
417 	"loadaddr=0x80100000\0"			\
418 	"kernel_addr=0x100000\0"		\
419 	"ramdisk_addr=0x800000\0"		\
420 	"ramdisk_size=0x2000000\0"		\
421 	"fdt_high=0xa0000000\0"			\
422 	"initrd_high=0xffffffffffffffff\0"	\
423 	"kernel_start=0x581000000\0"		\
424 	"kernel_load=0xa0000000\0"		\
425 	"kernel_size=0x2800000\0"		\
426 	"mcmemsize=0x40000000\0"		\
427 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
428 	"mcinitcmd=fsl_mc start mc 0x580a00000" \
429 	" 0x580e00000 \0"                       \
430 	BOOTENV
431 #endif
432 #endif
433 
434 
435 #undef CONFIG_BOOTARGS
436 #define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
437 				"earlycon=uart8250,mmio,0x21c0600 " \
438 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
439 				" hugepagesz=2m hugepages=256"
440 
441 #undef CONFIG_BOOTCOMMAND
442 #ifdef CONFIG_QSPI_BOOT
443 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
444 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
445 			   " && bootm $kernel_start" \
446 			   " || run distro_bootcmd"
447 #else
448 /* Try to boot an on-NOR kernel first, then do normal distro boot */
449 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
450 			   " && cp.b $kernel_start $kernel_load $kernel_size" \
451 			   " && bootm $kernel_load" \
452 			   " || run distro_bootcmd"
453 #endif
454 
455 /* MAC/PHY configuration */
456 #ifdef CONFIG_FSL_MC_ENET
457 #define CONFIG_PHYLIB_10G
458 #define CONFIG_PHY_AQUANTIA
459 #define CONFIG_PHY_CORTINA
460 #define CONFIG_PHYLIB
461 #define	CONFIG_SYS_CORTINA_FW_IN_NOR
462 #ifdef CONFIG_QSPI_BOOT
463 #define CONFIG_CORTINA_FW_ADDR		0x20980000
464 #else
465 #define CONFIG_CORTINA_FW_ADDR		0x580980000
466 #endif
467 #define CONFIG_CORTINA_FW_LENGTH	0x40000
468 
469 #define CORTINA_PHY_ADDR1	0x10
470 #define CORTINA_PHY_ADDR2	0x11
471 #define CORTINA_PHY_ADDR3	0x12
472 #define CORTINA_PHY_ADDR4	0x13
473 #define AQ_PHY_ADDR1		0x00
474 #define AQ_PHY_ADDR2		0x01
475 #define AQ_PHY_ADDR3		0x02
476 #define AQ_PHY_ADDR4		0x03
477 #define AQR405_IRQ_MASK		0x36
478 
479 #define CONFIG_MII
480 #define CONFIG_ETHPRIME		"DPMAC1@xgmii"
481 #define CONFIG_PHY_GIGE
482 #define CONFIG_PHY_AQUANTIA
483 #endif
484 
485 #include <asm/fsl_secure_boot.h>
486 
487 #endif /* __LS2_RDB_H */
488