1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_RDB_H 9 #define __LS2_RDB_H 10 11 #include "ls2080a_common.h" 12 13 #undef CONFIG_CONS_INDEX 14 #define CONFIG_CONS_INDEX 2 15 16 #ifdef CONFIG_FSL_QSPI 17 #ifdef CONFIG_TARGET_LS2081ARDB 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #endif 20 #define CONFIG_SYS_I2C_EARLY_INIT 21 #define CONFIG_DISPLAY_BOARDINFO_LATE 22 #endif 23 24 #define I2C_MUX_CH_VOL_MONITOR 0xa 25 #define I2C_VOL_MONITOR_ADDR 0x38 26 #define CONFIG_VOL_MONITOR_IR36021_READ 27 #define CONFIG_VOL_MONITOR_IR36021_SET 28 29 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 30 #ifndef CONFIG_SPL_BUILD 31 #define CONFIG_VID 32 #endif 33 /* step the IR regulator in 5mV increments */ 34 #define IR_VDD_STEP_DOWN 5 35 #define IR_VDD_STEP_UP 5 36 /* The lowest and highest voltage allowed for LS2080ARDB */ 37 #define VDD_MV_MIN 819 38 #define VDD_MV_MAX 1212 39 40 #ifndef __ASSEMBLY__ 41 unsigned long get_board_sys_clk(void); 42 #endif 43 44 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 45 #define CONFIG_DDR_CLK_FREQ 133333333 46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 47 48 #define CONFIG_DDR_SPD 49 #define CONFIG_DDR_ECC 50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 52 #define SPD_EEPROM_ADDRESS1 0x51 53 #define SPD_EEPROM_ADDRESS2 0x52 54 #define SPD_EEPROM_ADDRESS3 0x53 55 #define SPD_EEPROM_ADDRESS4 0x54 56 #define SPD_EEPROM_ADDRESS5 0x55 57 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 58 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 59 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 60 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 61 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 62 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 63 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 64 #endif 65 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 66 67 /* SATA */ 68 #define CONFIG_LIBATA 69 #define CONFIG_SCSI_AHCI 70 #define CONFIG_SCSI_AHCI_PLAT 71 72 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 73 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 74 75 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 76 #define CONFIG_SYS_SCSI_MAX_LUN 1 77 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 78 CONFIG_SYS_SCSI_MAX_LUN) 79 80 #ifndef CONFIG_FSL_QSPI 81 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 82 83 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 84 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 85 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 86 87 #define CONFIG_SYS_NOR0_CSPR \ 88 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 89 CSPR_PORT_SIZE_16 | \ 90 CSPR_MSEL_NOR | \ 91 CSPR_V) 92 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 93 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 94 CSPR_PORT_SIZE_16 | \ 95 CSPR_MSEL_NOR | \ 96 CSPR_V) 97 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 98 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 99 FTIM0_NOR_TEADC(0x5) | \ 100 FTIM0_NOR_TEAHC(0x5)) 101 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 102 FTIM1_NOR_TRAD_NOR(0x1a) |\ 103 FTIM1_NOR_TSEQRAD_NOR(0x13)) 104 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 105 FTIM2_NOR_TCH(0x4) | \ 106 FTIM2_NOR_TWPH(0x0E) | \ 107 FTIM2_NOR_TWP(0x1c)) 108 #define CONFIG_SYS_NOR_FTIM3 0x04000000 109 #define CONFIG_SYS_IFC_CCR 0x01000000 110 111 #ifdef CONFIG_MTD_NOR_FLASH 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 115 #define CONFIG_SYS_FLASH_QUIET_TEST 116 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 117 118 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 119 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_FLASH_EMPTY_INFO 124 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 125 CONFIG_SYS_FLASH_BASE + 0x40000000} 126 #endif 127 128 #define CONFIG_NAND_FSL_IFC 129 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 130 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 131 132 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 133 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 134 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 135 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 136 | CSPR_V) 137 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 138 139 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 140 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 141 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 142 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 143 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 144 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 145 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 146 147 #define CONFIG_SYS_NAND_ONFI_DETECTION 148 149 /* ONFI NAND Flash mode0 Timing Params */ 150 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 151 FTIM0_NAND_TWP(0x30) | \ 152 FTIM0_NAND_TWCHT(0x0e) | \ 153 FTIM0_NAND_TWH(0x14)) 154 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 155 FTIM1_NAND_TWBE(0xab) | \ 156 FTIM1_NAND_TRR(0x1c) | \ 157 FTIM1_NAND_TRP(0x30)) 158 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 159 FTIM2_NAND_TREH(0x14) | \ 160 FTIM2_NAND_TWHRE(0x3c)) 161 #define CONFIG_SYS_NAND_FTIM3 0x0 162 163 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 164 #define CONFIG_SYS_MAX_NAND_DEVICE 1 165 #define CONFIG_MTD_NAND_VERIFY_WRITE 166 #define CONFIG_CMD_NAND 167 168 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 169 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 170 #define QIXIS_LBMAP_SWITCH 0x06 171 #define QIXIS_LBMAP_MASK 0x0f 172 #define QIXIS_LBMAP_SHIFT 0 173 #define QIXIS_LBMAP_DFLTBANK 0x00 174 #define QIXIS_LBMAP_ALTBANK 0x04 175 #define QIXIS_LBMAP_NAND 0x09 176 #define QIXIS_RST_CTL_RESET 0x31 177 #define QIXIS_RST_CTL_RESET_EN 0x30 178 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 179 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 180 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 181 #define QIXIS_RCW_SRC_NAND 0x119 182 #define QIXIS_RST_FORCE_MEM 0x01 183 184 #define CONFIG_SYS_CSPR3_EXT (0x0) 185 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 186 | CSPR_PORT_SIZE_8 \ 187 | CSPR_MSEL_GPCM \ 188 | CSPR_V) 189 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 190 | CSPR_PORT_SIZE_8 \ 191 | CSPR_MSEL_GPCM \ 192 | CSPR_V) 193 194 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 195 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 196 /* QIXIS Timing parameters for IFC CS3 */ 197 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 198 FTIM0_GPCM_TEADC(0x0e) | \ 199 FTIM0_GPCM_TEAHC(0x0e)) 200 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 201 FTIM1_GPCM_TRAD(0x3f)) 202 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 203 FTIM2_GPCM_TCH(0xf) | \ 204 FTIM2_GPCM_TWP(0x3E)) 205 #define CONFIG_SYS_CS3_FTIM3 0x0 206 207 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 208 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 209 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 210 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 211 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 212 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 213 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 214 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 215 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 216 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 217 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 218 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 219 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 220 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 221 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 222 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 223 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 224 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 225 226 #define CONFIG_ENV_IS_IN_NAND 227 #define CONFIG_ENV_OFFSET (2048 * 1024) 228 #define CONFIG_ENV_SECT_SIZE 0x20000 229 #define CONFIG_ENV_SIZE 0x2000 230 #define CONFIG_SPL_PAD_TO 0x80000 231 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 233 #else 234 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 235 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 236 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 237 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 238 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 239 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 240 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 241 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 242 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 243 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 244 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 245 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 246 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 247 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 248 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 249 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 250 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 251 252 #define CONFIG_ENV_IS_IN_FLASH 253 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 254 #define CONFIG_ENV_SECT_SIZE 0x20000 255 #define CONFIG_ENV_SIZE 0x2000 256 #endif 257 258 /* Debug Server firmware */ 259 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 260 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 261 #endif 262 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 263 264 #ifdef CONFIG_TARGET_LS2081ARDB 265 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 266 #define QIXIS_QMAP_MASK 0x07 267 #define QIXIS_QMAP_SHIFT 5 268 #define QIXIS_LBMAP_DFLTBANK 0x00 269 #define QIXIS_LBMAP_QSPI 0x00 270 #define QIXIS_RCW_SRC_QSPI 0x62 271 #define QIXIS_LBMAP_ALTBANK 0x20 272 #define QIXIS_RST_CTL_RESET 0x31 273 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 274 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 275 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 276 #define QIXIS_LBMAP_MASK 0x0f 277 #define QIXIS_RST_CTL_RESET_EN 0x30 278 #endif 279 280 /* 281 * I2C 282 */ 283 #ifdef CONFIG_TARGET_LS2081ARDB 284 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 285 #endif 286 #define I2C_MUX_PCA_ADDR 0x75 287 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 288 289 /* I2C bus multiplexer */ 290 #define I2C_MUX_CH_DEFAULT 0x8 291 292 /* SPI */ 293 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 294 #define CONFIG_SPI_FLASH 295 #ifdef CONFIG_FSL_QSPI 296 #define CONFIG_SPI_FLASH_STMICRO 297 #endif 298 #ifdef CONFIG_FSL_QSPI 299 #ifdef CONFIG_TARGET_LS2081ARDB 300 #define CONFIG_SPI_FLASH_STMICRO 301 #else 302 #define CONFIG_SPI_FLASH_SPANSION 303 #endif 304 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 305 #define FSL_QSPI_FLASH_NUM 2 306 #endif 307 #endif 308 309 /* 310 * RTC configuration 311 */ 312 #define RTC 313 #ifdef CONFIG_TARGET_LS2081ARDB 314 #define CONFIG_RTC_PCF8563 1 315 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 316 #else 317 #define CONFIG_RTC_DS3231 1 318 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 319 #endif 320 321 /* EEPROM */ 322 #define CONFIG_ID_EEPROM 323 #define CONFIG_SYS_I2C_EEPROM_NXID 324 #define CONFIG_SYS_EEPROM_BUS_NUM 0 325 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 326 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 329 330 #define CONFIG_FSL_MEMAC 331 332 #ifdef CONFIG_PCI 333 #define CONFIG_PCI_SCAN_SHOW 334 #define CONFIG_CMD_PCI 335 #endif 336 337 /* MMC */ 338 #ifdef CONFIG_MMC 339 #define CONFIG_FSL_ESDHC 340 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 341 #endif 342 343 #define CONFIG_MISC_INIT_R 344 345 /* 346 * USB 347 */ 348 #define CONFIG_HAS_FSL_XHCI_USB 349 #define CONFIG_USB_XHCI_FSL 350 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 351 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 352 353 #undef CONFIG_CMDLINE_EDITING 354 #include <config_distro_defaults.h> 355 356 #define BOOT_TARGET_DEVICES(func) \ 357 func(USB, usb, 0) \ 358 func(MMC, mmc, 0) \ 359 func(SCSI, scsi, 0) \ 360 func(DHCP, dhcp, na) 361 #include <config_distro_bootcmd.h> 362 363 /* Initial environment variables */ 364 #undef CONFIG_EXTRA_ENV_SETTINGS 365 #ifdef CONFIG_SECURE_BOOT 366 #define CONFIG_EXTRA_ENV_SETTINGS \ 367 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 368 "scriptaddr=0x80800000\0" \ 369 "kernel_addr_r=0x81000000\0" \ 370 "pxefile_addr_r=0x81000000\0" \ 371 "fdt_addr_r=0x88000000\0" \ 372 "ramdisk_addr_r=0x89000000\0" \ 373 "loadaddr=0x80100000\0" \ 374 "kernel_addr=0x100000\0" \ 375 "ramdisk_addr=0x800000\0" \ 376 "ramdisk_size=0x2000000\0" \ 377 "fdt_high=0xa0000000\0" \ 378 "initrd_high=0xffffffffffffffff\0" \ 379 "kernel_start=0x581000000\0" \ 380 "kernel_load=0xa0000000\0" \ 381 "kernel_size=0x2800000\0" \ 382 "mcmemsize=0x40000000\0" \ 383 "fdtfile=fsl-ls2080a-rdb.dtb\0" \ 384 "mcinitcmd=esbc_validate 0x580700000;" \ 385 "esbc_validate 0x580740000;" \ 386 "fsl_mc start mc 0x580a00000" \ 387 " 0x580e00000 \0" \ 388 BOOTENV 389 #else 390 #ifdef CONFIG_QSPI_BOOT 391 #define CONFIG_EXTRA_ENV_SETTINGS \ 392 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 393 "scriptaddr=0x80800000\0" \ 394 "kernel_addr_r=0x81000000\0" \ 395 "pxefile_addr_r=0x81000000\0" \ 396 "fdt_addr_r=0x88000000\0" \ 397 "ramdisk_addr_r=0x89000000\0" \ 398 "loadaddr=0x80100000\0" \ 399 "kernel_addr=0x100000\0" \ 400 "ramdisk_size=0x2000000\0" \ 401 "fdt_high=0xa0000000\0" \ 402 "initrd_high=0xffffffffffffffff\0" \ 403 "kernel_start=0x21000000\0" \ 404 "mcmemsize=0x40000000\0" \ 405 "mcinitcmd=fsl_mc start mc 0x20a00000" \ 406 " 0x20e00000 \0" \ 407 BOOTENV 408 #else 409 #define CONFIG_EXTRA_ENV_SETTINGS \ 410 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 411 "scriptaddr=0x80800000\0" \ 412 "kernel_addr_r=0x81000000\0" \ 413 "pxefile_addr_r=0x81000000\0" \ 414 "fdt_addr_r=0x88000000\0" \ 415 "ramdisk_addr_r=0x89000000\0" \ 416 "loadaddr=0x80100000\0" \ 417 "kernel_addr=0x100000\0" \ 418 "ramdisk_addr=0x800000\0" \ 419 "ramdisk_size=0x2000000\0" \ 420 "fdt_high=0xa0000000\0" \ 421 "initrd_high=0xffffffffffffffff\0" \ 422 "kernel_start=0x581000000\0" \ 423 "kernel_load=0xa0000000\0" \ 424 "kernel_size=0x2800000\0" \ 425 "mcmemsize=0x40000000\0" \ 426 "fdtfile=fsl-ls2080a-rdb.dtb\0" \ 427 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 428 " 0x580e00000 \0" \ 429 BOOTENV 430 #endif 431 #endif 432 433 434 #undef CONFIG_BOOTARGS 435 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ 436 "earlycon=uart8250,mmio,0x21c0600 " \ 437 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 438 " hugepagesz=2m hugepages=256" 439 440 #undef CONFIG_BOOTCOMMAND 441 #ifdef CONFIG_QSPI_BOOT 442 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 443 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \ 444 " && bootm $kernel_start" \ 445 " || run distro_bootcmd" 446 #else 447 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 448 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \ 449 " && cp.b $kernel_start $kernel_load $kernel_size" \ 450 " && bootm $kernel_load" \ 451 " || run distro_bootcmd" 452 #endif 453 454 /* MAC/PHY configuration */ 455 #ifdef CONFIG_FSL_MC_ENET 456 #define CONFIG_PHYLIB_10G 457 #define CONFIG_PHY_AQUANTIA 458 #define CONFIG_PHY_CORTINA 459 #define CONFIG_PHYLIB 460 #define CONFIG_SYS_CORTINA_FW_IN_NOR 461 #ifdef CONFIG_QSPI_BOOT 462 #define CONFIG_CORTINA_FW_ADDR 0x20980000 463 #else 464 #define CONFIG_CORTINA_FW_ADDR 0x580980000 465 #endif 466 #define CONFIG_CORTINA_FW_LENGTH 0x40000 467 468 #define CORTINA_PHY_ADDR1 0x10 469 #define CORTINA_PHY_ADDR2 0x11 470 #define CORTINA_PHY_ADDR3 0x12 471 #define CORTINA_PHY_ADDR4 0x13 472 #define AQ_PHY_ADDR1 0x00 473 #define AQ_PHY_ADDR2 0x01 474 #define AQ_PHY_ADDR3 0x02 475 #define AQ_PHY_ADDR4 0x03 476 #define AQR405_IRQ_MASK 0x36 477 478 #define CONFIG_MII 479 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 480 #define CONFIG_PHY_GIGE 481 #define CONFIG_PHY_AQUANTIA 482 #endif 483 484 #include <asm/fsl_secure_boot.h> 485 486 #endif /* __LS2_RDB_H */ 487