1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_RDB_H 9 #define __LS2_RDB_H 10 11 #include "ls2080a_common.h" 12 13 #undef CONFIG_CONS_INDEX 14 #define CONFIG_CONS_INDEX 2 15 16 #ifdef CONFIG_FSL_QSPI 17 #ifdef CONFIG_TARGET_LS2081ARDB 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #endif 20 #define CONFIG_SYS_I2C_EARLY_INIT 21 #endif 22 23 #define I2C_MUX_CH_VOL_MONITOR 0xa 24 #define I2C_VOL_MONITOR_ADDR 0x38 25 #define CONFIG_VOL_MONITOR_IR36021_READ 26 #define CONFIG_VOL_MONITOR_IR36021_SET 27 28 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 29 #ifndef CONFIG_SPL_BUILD 30 #define CONFIG_VID 31 #endif 32 /* step the IR regulator in 5mV increments */ 33 #define IR_VDD_STEP_DOWN 5 34 #define IR_VDD_STEP_UP 5 35 /* The lowest and highest voltage allowed for LS2080ARDB */ 36 #define VDD_MV_MIN 819 37 #define VDD_MV_MAX 1212 38 39 #ifndef __ASSEMBLY__ 40 unsigned long get_board_sys_clk(void); 41 #endif 42 43 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 44 #define CONFIG_DDR_CLK_FREQ 133333333 45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 46 47 #define CONFIG_DDR_SPD 48 #define CONFIG_DDR_ECC 49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 51 #define SPD_EEPROM_ADDRESS1 0x51 52 #define SPD_EEPROM_ADDRESS2 0x52 53 #define SPD_EEPROM_ADDRESS3 0x53 54 #define SPD_EEPROM_ADDRESS4 0x54 55 #define SPD_EEPROM_ADDRESS5 0x55 56 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 57 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 58 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 59 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 60 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 61 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 62 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 63 #endif 64 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 65 66 /* SATA */ 67 #define CONFIG_LIBATA 68 #define CONFIG_SCSI_AHCI 69 #define CONFIG_SCSI_AHCI_PLAT 70 71 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 72 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 73 74 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 75 #define CONFIG_SYS_SCSI_MAX_LUN 1 76 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 77 CONFIG_SYS_SCSI_MAX_LUN) 78 79 #ifndef CONFIG_FSL_QSPI 80 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 81 82 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 83 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 84 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 85 86 #define CONFIG_SYS_NOR0_CSPR \ 87 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 88 CSPR_PORT_SIZE_16 | \ 89 CSPR_MSEL_NOR | \ 90 CSPR_V) 91 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 92 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 93 CSPR_PORT_SIZE_16 | \ 94 CSPR_MSEL_NOR | \ 95 CSPR_V) 96 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 97 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 98 FTIM0_NOR_TEADC(0x5) | \ 99 FTIM0_NOR_TEAHC(0x5)) 100 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 101 FTIM1_NOR_TRAD_NOR(0x1a) |\ 102 FTIM1_NOR_TSEQRAD_NOR(0x13)) 103 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 104 FTIM2_NOR_TCH(0x4) | \ 105 FTIM2_NOR_TWPH(0x0E) | \ 106 FTIM2_NOR_TWP(0x1c)) 107 #define CONFIG_SYS_NOR_FTIM3 0x04000000 108 #define CONFIG_SYS_IFC_CCR 0x01000000 109 110 #ifdef CONFIG_MTD_NOR_FLASH 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #define CONFIG_SYS_FLASH_QUIET_TEST 115 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 116 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 122 #define CONFIG_SYS_FLASH_EMPTY_INFO 123 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 124 CONFIG_SYS_FLASH_BASE + 0x40000000} 125 #endif 126 127 #define CONFIG_NAND_FSL_IFC 128 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 129 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 130 131 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 132 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 133 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 134 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 135 | CSPR_V) 136 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 137 138 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 139 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 140 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 141 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 142 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 143 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 144 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 145 146 #define CONFIG_SYS_NAND_ONFI_DETECTION 147 148 /* ONFI NAND Flash mode0 Timing Params */ 149 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 150 FTIM0_NAND_TWP(0x30) | \ 151 FTIM0_NAND_TWCHT(0x0e) | \ 152 FTIM0_NAND_TWH(0x14)) 153 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 154 FTIM1_NAND_TWBE(0xab) | \ 155 FTIM1_NAND_TRR(0x1c) | \ 156 FTIM1_NAND_TRP(0x30)) 157 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 158 FTIM2_NAND_TREH(0x14) | \ 159 FTIM2_NAND_TWHRE(0x3c)) 160 #define CONFIG_SYS_NAND_FTIM3 0x0 161 162 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 164 #define CONFIG_MTD_NAND_VERIFY_WRITE 165 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 167 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 168 #define QIXIS_LBMAP_SWITCH 0x06 169 #define QIXIS_LBMAP_MASK 0x0f 170 #define QIXIS_LBMAP_SHIFT 0 171 #define QIXIS_LBMAP_DFLTBANK 0x00 172 #define QIXIS_LBMAP_ALTBANK 0x04 173 #define QIXIS_LBMAP_NAND 0x09 174 #define QIXIS_RST_CTL_RESET 0x31 175 #define QIXIS_RST_CTL_RESET_EN 0x30 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 179 #define QIXIS_RCW_SRC_NAND 0x119 180 #define QIXIS_RST_FORCE_MEM 0x01 181 182 #define CONFIG_SYS_CSPR3_EXT (0x0) 183 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 184 | CSPR_PORT_SIZE_8 \ 185 | CSPR_MSEL_GPCM \ 186 | CSPR_V) 187 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 188 | CSPR_PORT_SIZE_8 \ 189 | CSPR_MSEL_GPCM \ 190 | CSPR_V) 191 192 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 193 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 194 /* QIXIS Timing parameters for IFC CS3 */ 195 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 196 FTIM0_GPCM_TEADC(0x0e) | \ 197 FTIM0_GPCM_TEAHC(0x0e)) 198 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 199 FTIM1_GPCM_TRAD(0x3f)) 200 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 201 FTIM2_GPCM_TCH(0xf) | \ 202 FTIM2_GPCM_TWP(0x3E)) 203 #define CONFIG_SYS_CS3_FTIM3 0x0 204 205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 206 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 207 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 208 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 209 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 223 224 #define CONFIG_ENV_OFFSET (2048 * 1024) 225 #define CONFIG_ENV_SECT_SIZE 0x20000 226 #define CONFIG_ENV_SIZE 0x2000 227 #define CONFIG_SPL_PAD_TO 0x80000 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 229 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 230 #else 231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 233 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 236 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 237 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 238 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 239 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 240 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 241 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 242 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 243 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 244 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 245 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 246 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 247 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 248 249 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 250 #define CONFIG_ENV_SECT_SIZE 0x20000 251 #define CONFIG_ENV_SIZE 0x2000 252 #endif 253 254 /* Debug Server firmware */ 255 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 256 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 257 #endif 258 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 259 260 #ifdef CONFIG_TARGET_LS2081ARDB 261 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 262 #define QIXIS_QMAP_MASK 0x07 263 #define QIXIS_QMAP_SHIFT 5 264 #define QIXIS_LBMAP_DFLTBANK 0x00 265 #define QIXIS_LBMAP_QSPI 0x00 266 #define QIXIS_RCW_SRC_QSPI 0x62 267 #define QIXIS_LBMAP_ALTBANK 0x20 268 #define QIXIS_RST_CTL_RESET 0x31 269 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 270 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 271 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 272 #define QIXIS_LBMAP_MASK 0x0f 273 #define QIXIS_RST_CTL_RESET_EN 0x30 274 #endif 275 276 /* 277 * I2C 278 */ 279 #ifdef CONFIG_TARGET_LS2081ARDB 280 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 281 #endif 282 #define I2C_MUX_PCA_ADDR 0x75 283 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 284 285 /* I2C bus multiplexer */ 286 #define I2C_MUX_CH_DEFAULT 0x8 287 288 /* SPI */ 289 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 290 #define CONFIG_SPI_FLASH 291 #ifdef CONFIG_FSL_DSPI 292 #define CONFIG_SPI_FLASH_STMICRO 293 #endif 294 #ifdef CONFIG_FSL_QSPI 295 #define CONFIG_SPI_FLASH_SPANSION 296 #endif 297 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 298 #define FSL_QSPI_FLASH_NUM 2 299 #endif 300 301 /* 302 * RTC configuration 303 */ 304 #define RTC 305 #ifdef CONFIG_TARGET_LS2081ARDB 306 #define CONFIG_RTC_PCF8563 1 307 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 308 #else 309 #define CONFIG_RTC_DS3231 1 310 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 311 #endif 312 313 /* EEPROM */ 314 #define CONFIG_ID_EEPROM 315 #define CONFIG_SYS_I2C_EEPROM_NXID 316 #define CONFIG_SYS_EEPROM_BUS_NUM 0 317 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 321 322 #define CONFIG_FSL_MEMAC 323 324 #ifdef CONFIG_PCI 325 #define CONFIG_PCI_SCAN_SHOW 326 #endif 327 328 /* MMC */ 329 #ifdef CONFIG_MMC 330 #define CONFIG_FSL_ESDHC 331 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 332 #endif 333 334 #define CONFIG_MISC_INIT_R 335 336 #undef CONFIG_CMDLINE_EDITING 337 #include <config_distro_defaults.h> 338 339 #define BOOT_TARGET_DEVICES(func) \ 340 func(USB, usb, 0) \ 341 func(MMC, mmc, 0) \ 342 func(SCSI, scsi, 0) \ 343 func(DHCP, dhcp, na) 344 #include <config_distro_bootcmd.h> 345 346 #ifdef CONFIG_QSPI_BOOT 347 #define MC_INIT_CMD \ 348 "mcinitcmd=env exists secureboot && " \ 349 "esbc_validate 0x20700000 && " \ 350 "esbc_validate 0x20740000;" \ 351 "fsl_mc start mc 0x20a00000 0x20e00000 \0" 352 #else 353 #define MC_INIT_CMD \ 354 "mcinitcmd=env exists secureboot && " \ 355 "esbc_validate 0x580700000 && " \ 356 "esbc_validate 0x580740000; " \ 357 "fsl_mc start mc 0x580a00000 0x580e00000 \0" 358 #endif 359 360 /* Initial environment variables */ 361 #undef CONFIG_EXTRA_ENV_SETTINGS 362 #define CONFIG_EXTRA_ENV_SETTINGS \ 363 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 364 "ramdisk_addr=0x800000\0" \ 365 "ramdisk_size=0x2000000\0" \ 366 "fdt_high=0xa0000000\0" \ 367 "initrd_high=0xffffffffffffffff\0" \ 368 "fdt_addr=0x64f00000\0" \ 369 "kernel_addr=0x65000000\0" \ 370 "kernel_start=0x1000000\0" \ 371 "kernelheader_start=0x800000\0" \ 372 "scriptaddr=0x80000000\0" \ 373 "scripthdraddr=0x80080000\0" \ 374 "fdtheader_addr_r=0x80100000\0" \ 375 "kernelheader_addr_r=0x80200000\0" \ 376 "kernelheader_addr=0x580800000\0" \ 377 "kernel_addr_r=0x81000000\0" \ 378 "kernelheader_size=0x40000\0" \ 379 "fdt_addr_r=0x90000000\0" \ 380 "load_addr=0xa0000000\0" \ 381 "kernel_size=0x2800000\0" \ 382 "console=ttyAMA0,38400n8\0" \ 383 "mcmemsize=0x70000000\0" \ 384 MC_INIT_CMD \ 385 BOOTENV \ 386 "boot_scripts=ls2088ardb_boot.scr\0" \ 387 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ 388 "scan_dev_for_boot_part=" \ 389 "part list ${devtype} ${devnum} devplist; " \ 390 "env exists devplist || setenv devplist 1; " \ 391 "for distro_bootpart in ${devplist}; do " \ 392 "if fstype ${devtype} " \ 393 "${devnum}:${distro_bootpart} " \ 394 "bootfstype; then " \ 395 "run scan_dev_for_boot; " \ 396 "fi; " \ 397 "done\0" \ 398 "scan_dev_for_boot=" \ 399 "echo Scanning ${devtype} " \ 400 "${devnum}:${distro_bootpart}...; " \ 401 "for prefix in ${boot_prefixes}; do " \ 402 "run scan_dev_for_scripts; " \ 403 "done;\0" \ 404 "boot_a_script=" \ 405 "load ${devtype} ${devnum}:${distro_bootpart} " \ 406 "${scriptaddr} ${prefix}${script}; " \ 407 "env exists secureboot && load ${devtype} " \ 408 "${devnum}:${distro_bootpart} " \ 409 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 410 "&& esbc_validate ${scripthdraddr};" \ 411 "source ${scriptaddr}\0" \ 412 "installer=load mmc 0:2 $load_addr " \ 413 "/flex_installer_arm64.itb; " \ 414 "bootm $load_addr#ls2088ardb\0" \ 415 "qspi_bootcmd=echo Trying load from qspi..;" \ 416 "sf probe && sf read $load_addr " \ 417 "$kernel_start $kernel_size ; env exists secureboot &&" \ 418 "sf read $kernelheader_addr_r $kernelheader_start " \ 419 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 420 " bootm $load_addr#$board\0" \ 421 "nor_bootcmd=echo Trying load from nor..;" \ 422 "cp.b $kernel_addr $load_addr " \ 423 "$kernel_size ; env exists secureboot && " \ 424 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 425 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 426 "bootm $load_addr#$board\0" 427 428 #undef CONFIG_BOOTCOMMAND 429 #ifdef CONFIG_QSPI_BOOT 430 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 431 #define CONFIG_BOOTCOMMAND \ 432 "env exists mcinitcmd && env exists secureboot "\ 433 "&& esbc_validate 0x20780000; " \ 434 "env exists mcinitcmd && " \ 435 "fsl_mc lazyapply dpl 0x20d00000; " \ 436 "run distro_bootcmd;run qspi_bootcmd; " \ 437 "env exists secureboot && esbc_halt; " 438 #else 439 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 440 #define CONFIG_BOOTCOMMAND \ 441 "env exists mcinitcmd && env exists secureboot "\ 442 "&& esbc_validate 0x580780000; env exists mcinitcmd "\ 443 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 444 "run distro_bootcmd;run nor_bootcmd; " \ 445 "env exists secureboot && esbc_halt; " 446 #endif 447 448 /* MAC/PHY configuration */ 449 #ifdef CONFIG_FSL_MC_ENET 450 #define CONFIG_PHYLIB_10G 451 #define CONFIG_PHY_AQUANTIA 452 #define CONFIG_PHY_CORTINA 453 #define CONFIG_SYS_CORTINA_FW_IN_NOR 454 #ifdef CONFIG_QSPI_BOOT 455 #define CONFIG_CORTINA_FW_ADDR 0x20980000 456 #else 457 #define CONFIG_CORTINA_FW_ADDR 0x580980000 458 #endif 459 #define CONFIG_CORTINA_FW_LENGTH 0x40000 460 461 #define CORTINA_PHY_ADDR1 0x10 462 #define CORTINA_PHY_ADDR2 0x11 463 #define CORTINA_PHY_ADDR3 0x12 464 #define CORTINA_PHY_ADDR4 0x13 465 #define AQ_PHY_ADDR1 0x00 466 #define AQ_PHY_ADDR2 0x01 467 #define AQ_PHY_ADDR3 0x02 468 #define AQ_PHY_ADDR4 0x03 469 #define AQR405_IRQ_MASK 0x36 470 471 #define CONFIG_MII 472 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 473 #define CONFIG_PHY_AQUANTIA 474 #endif 475 476 #include <asm/fsl_secure_boot.h> 477 478 #endif /* __LS2_RDB_H */ 479