1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_RDB_H 9 #define __LS2_RDB_H 10 11 #include "ls2080a_common.h" 12 13 #ifdef CONFIG_FSL_QSPI 14 #ifdef CONFIG_TARGET_LS2081ARDB 15 #define CONFIG_QIXIS_I2C_ACCESS 16 #endif 17 #define CONFIG_SYS_I2C_EARLY_INIT 18 #endif 19 20 #define I2C_MUX_CH_VOL_MONITOR 0xa 21 #define I2C_VOL_MONITOR_ADDR 0x38 22 #define CONFIG_VOL_MONITOR_IR36021_READ 23 #define CONFIG_VOL_MONITOR_IR36021_SET 24 25 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" 26 #ifndef CONFIG_SPL_BUILD 27 #define CONFIG_VID 28 #endif 29 /* step the IR regulator in 5mV increments */ 30 #define IR_VDD_STEP_DOWN 5 31 #define IR_VDD_STEP_UP 5 32 /* The lowest and highest voltage allowed for LS2080ARDB */ 33 #define VDD_MV_MIN 819 34 #define VDD_MV_MAX 1212 35 36 #ifndef __ASSEMBLY__ 37 unsigned long get_board_sys_clk(void); 38 #endif 39 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_DDR_CLK_FREQ 133333333 42 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 43 44 #define CONFIG_DDR_SPD 45 #define CONFIG_DDR_ECC 46 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 48 #define SPD_EEPROM_ADDRESS1 0x51 49 #define SPD_EEPROM_ADDRESS2 0x52 50 #define SPD_EEPROM_ADDRESS3 0x53 51 #define SPD_EEPROM_ADDRESS4 0x54 52 #define SPD_EEPROM_ADDRESS5 0x55 53 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 54 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 55 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 56 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 57 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 58 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 59 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 60 #endif 61 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 62 63 /* SATA */ 64 #define CONFIG_SCSI_AHCI_PLAT 65 66 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 67 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 68 69 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 70 #define CONFIG_SYS_SCSI_MAX_LUN 1 71 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 72 CONFIG_SYS_SCSI_MAX_LUN) 73 74 #ifndef CONFIG_FSL_QSPI 75 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 76 77 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 78 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 79 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 80 81 #define CONFIG_SYS_NOR0_CSPR \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 83 CSPR_PORT_SIZE_16 | \ 84 CSPR_MSEL_NOR | \ 85 CSPR_V) 86 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 87 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 88 CSPR_PORT_SIZE_16 | \ 89 CSPR_MSEL_NOR | \ 90 CSPR_V) 91 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 92 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 93 FTIM0_NOR_TEADC(0x5) | \ 94 FTIM0_NOR_TEAHC(0x5)) 95 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 96 FTIM1_NOR_TRAD_NOR(0x1a) |\ 97 FTIM1_NOR_TSEQRAD_NOR(0x13)) 98 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 99 FTIM2_NOR_TCH(0x4) | \ 100 FTIM2_NOR_TWPH(0x0E) | \ 101 FTIM2_NOR_TWP(0x1c)) 102 #define CONFIG_SYS_NOR_FTIM3 0x04000000 103 #define CONFIG_SYS_IFC_CCR 0x01000000 104 105 #ifdef CONFIG_MTD_NOR_FLASH 106 #define CONFIG_FLASH_CFI_DRIVER 107 #define CONFIG_SYS_FLASH_CFI 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 #define CONFIG_SYS_FLASH_QUIET_TEST 110 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 111 112 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 113 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 116 117 #define CONFIG_SYS_FLASH_EMPTY_INFO 118 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 119 CONFIG_SYS_FLASH_BASE + 0x40000000} 120 #endif 121 122 #define CONFIG_NAND_FSL_IFC 123 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 124 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 125 126 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 127 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 128 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 129 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 130 | CSPR_V) 131 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 132 133 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 134 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 135 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 136 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 137 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 138 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 139 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ 140 141 #define CONFIG_SYS_NAND_ONFI_DETECTION 142 143 /* ONFI NAND Flash mode0 Timing Params */ 144 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ 145 FTIM0_NAND_TWP(0x30) | \ 146 FTIM0_NAND_TWCHT(0x0e) | \ 147 FTIM0_NAND_TWH(0x14)) 148 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ 149 FTIM1_NAND_TWBE(0xab) | \ 150 FTIM1_NAND_TRR(0x1c) | \ 151 FTIM1_NAND_TRP(0x30)) 152 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ 153 FTIM2_NAND_TREH(0x14) | \ 154 FTIM2_NAND_TWHRE(0x3c)) 155 #define CONFIG_SYS_NAND_FTIM3 0x0 156 157 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 159 #define CONFIG_MTD_NAND_VERIFY_WRITE 160 161 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 163 #define QIXIS_LBMAP_SWITCH 0x06 164 #define QIXIS_LBMAP_MASK 0x0f 165 #define QIXIS_LBMAP_SHIFT 0 166 #define QIXIS_LBMAP_DFLTBANK 0x00 167 #define QIXIS_LBMAP_ALTBANK 0x04 168 #define QIXIS_LBMAP_NAND 0x09 169 #define QIXIS_RST_CTL_RESET 0x31 170 #define QIXIS_RST_CTL_RESET_EN 0x30 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 174 #define QIXIS_RCW_SRC_NAND 0x119 175 #define QIXIS_RST_FORCE_MEM 0x01 176 177 #define CONFIG_SYS_CSPR3_EXT (0x0) 178 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 179 | CSPR_PORT_SIZE_8 \ 180 | CSPR_MSEL_GPCM \ 181 | CSPR_V) 182 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 183 | CSPR_PORT_SIZE_8 \ 184 | CSPR_MSEL_GPCM \ 185 | CSPR_V) 186 187 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 188 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 189 /* QIXIS Timing parameters for IFC CS3 */ 190 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 191 FTIM0_GPCM_TEADC(0x0e) | \ 192 FTIM0_GPCM_TEAHC(0x0e)) 193 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 194 FTIM1_GPCM_TRAD(0x3f)) 195 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 196 FTIM2_GPCM_TCH(0xf) | \ 197 FTIM2_GPCM_TWP(0x3E)) 198 #define CONFIG_SYS_CS3_FTIM3 0x0 199 200 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 201 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 202 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY 203 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR 204 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 205 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 206 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 207 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 208 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 209 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 210 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 211 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 212 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 213 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 214 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 215 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 216 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 217 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 218 219 #define CONFIG_ENV_OFFSET (2048 * 1024) 220 #define CONFIG_ENV_SECT_SIZE 0x20000 221 #define CONFIG_ENV_SIZE 0x2000 222 #define CONFIG_SPL_PAD_TO 0x80000 223 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) 224 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 225 #else 226 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 227 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 228 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 229 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 230 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 231 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 232 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 233 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 234 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 235 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 236 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 237 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 238 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 239 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 240 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 241 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 242 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 243 244 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 245 #define CONFIG_ENV_SECT_SIZE 0x20000 246 #define CONFIG_ENV_SIZE 0x2000 247 #endif 248 249 /* Debug Server firmware */ 250 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 251 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 252 #endif 253 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 254 255 #ifdef CONFIG_TARGET_LS2081ARDB 256 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 257 #define QIXIS_QMAP_MASK 0x07 258 #define QIXIS_QMAP_SHIFT 5 259 #define QIXIS_LBMAP_DFLTBANK 0x00 260 #define QIXIS_LBMAP_QSPI 0x00 261 #define QIXIS_RCW_SRC_QSPI 0x62 262 #define QIXIS_LBMAP_ALTBANK 0x20 263 #define QIXIS_RST_CTL_RESET 0x31 264 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 265 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 266 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 267 #define QIXIS_LBMAP_MASK 0x0f 268 #define QIXIS_RST_CTL_RESET_EN 0x30 269 #endif 270 271 /* 272 * I2C 273 */ 274 #ifdef CONFIG_TARGET_LS2081ARDB 275 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 276 #endif 277 #define I2C_MUX_PCA_ADDR 0x75 278 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ 279 280 /* I2C bus multiplexer */ 281 #define I2C_MUX_CH_DEFAULT 0x8 282 283 /* SPI */ 284 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 285 #define CONFIG_SPI_FLASH 286 #ifdef CONFIG_FSL_DSPI 287 #define CONFIG_SPI_FLASH_STMICRO 288 #endif 289 #ifdef CONFIG_FSL_QSPI 290 #define CONFIG_SPI_FLASH_SPANSION 291 #endif 292 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ 293 #define FSL_QSPI_FLASH_NUM 2 294 #endif 295 296 /* 297 * RTC configuration 298 */ 299 #define RTC 300 #ifdef CONFIG_TARGET_LS2081ARDB 301 #define CONFIG_RTC_PCF8563 1 302 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 303 #else 304 #define CONFIG_RTC_DS3231 1 305 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 306 #endif 307 308 /* EEPROM */ 309 #define CONFIG_ID_EEPROM 310 #define CONFIG_SYS_I2C_EEPROM_NXID 311 #define CONFIG_SYS_EEPROM_BUS_NUM 0 312 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 316 317 #define CONFIG_FSL_MEMAC 318 319 #ifdef CONFIG_PCI 320 #define CONFIG_PCI_SCAN_SHOW 321 #endif 322 323 /* MMC */ 324 #ifdef CONFIG_MMC 325 #define CONFIG_FSL_ESDHC 326 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 327 #endif 328 329 #define CONFIG_MISC_INIT_R 330 331 #define BOOT_TARGET_DEVICES(func) \ 332 func(USB, usb, 0) \ 333 func(MMC, mmc, 0) \ 334 func(SCSI, scsi, 0) \ 335 func(DHCP, dhcp, na) 336 #include <config_distro_bootcmd.h> 337 338 #ifdef CONFIG_QSPI_BOOT 339 #define MC_INIT_CMD \ 340 "mcinitcmd=env exists secureboot && " \ 341 "esbc_validate 0x20700000 && " \ 342 "esbc_validate 0x20740000;" \ 343 "fsl_mc start mc 0x20a00000 0x20e00000 \0" 344 #elif defined(CONFIG_SD_BOOT) 345 #define MC_INIT_CMD \ 346 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 347 "mmc read 0x80100000 0x7000 0x800;" \ 348 "env exists secureboot && " \ 349 "mmc read 0x80700000 0x3800 0x10 && " \ 350 "mmc read 0x80740000 0x3A00 0x10 && " \ 351 "esbc_validate 0x80700000 && " \ 352 "esbc_validate 0x80740000 ;" \ 353 "fsl_mc start mc 0x80000000 0x80100000\0" \ 354 "mcmemsize=0x70000000\0" 355 #else 356 #define MC_INIT_CMD \ 357 "mcinitcmd=env exists secureboot && " \ 358 "esbc_validate 0x580700000 && " \ 359 "esbc_validate 0x580740000; " \ 360 "fsl_mc start mc 0x580a00000 0x580e00000 \0" 361 #endif 362 363 /* Initial environment variables */ 364 #undef CONFIG_EXTRA_ENV_SETTINGS 365 #define CONFIG_EXTRA_ENV_SETTINGS \ 366 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 367 "ramdisk_addr=0x800000\0" \ 368 "ramdisk_size=0x2000000\0" \ 369 "fdt_high=0xa0000000\0" \ 370 "initrd_high=0xffffffffffffffff\0" \ 371 "fdt_addr=0x64f00000\0" \ 372 "kernel_addr=0x581000000\0" \ 373 "kernel_start=0x1000000\0" \ 374 "kernelheader_start=0x800000\0" \ 375 "scriptaddr=0x80000000\0" \ 376 "scripthdraddr=0x80080000\0" \ 377 "fdtheader_addr_r=0x80100000\0" \ 378 "kernelheader_addr_r=0x80200000\0" \ 379 "kernelheader_addr=0x580800000\0" \ 380 "kernel_addr_r=0x81000000\0" \ 381 "kernelheader_size=0x40000\0" \ 382 "fdt_addr_r=0x90000000\0" \ 383 "load_addr=0xa0000000\0" \ 384 "kernel_size=0x2800000\0" \ 385 "kernel_addr_sd=0x8000\0" \ 386 "kernel_size_sd=0x14000\0" \ 387 "console=ttyAMA0,38400n8\0" \ 388 "mcmemsize=0x70000000\0" \ 389 "sd_bootcmd=echo Trying load from SD ..;" \ 390 "mmcinfo; mmc read $load_addr " \ 391 "$kernel_addr_sd $kernel_size_sd && " \ 392 "bootm $load_addr#$board\0" \ 393 MC_INIT_CMD \ 394 BOOTENV \ 395 "boot_scripts=ls2088ardb_boot.scr\0" \ 396 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ 397 "scan_dev_for_boot_part=" \ 398 "part list ${devtype} ${devnum} devplist; " \ 399 "env exists devplist || setenv devplist 1; " \ 400 "for distro_bootpart in ${devplist}; do " \ 401 "if fstype ${devtype} " \ 402 "${devnum}:${distro_bootpart} " \ 403 "bootfstype; then " \ 404 "run scan_dev_for_boot; " \ 405 "fi; " \ 406 "done\0" \ 407 "scan_dev_for_boot=" \ 408 "echo Scanning ${devtype} " \ 409 "${devnum}:${distro_bootpart}...; " \ 410 "for prefix in ${boot_prefixes}; do " \ 411 "run scan_dev_for_scripts; " \ 412 "done;\0" \ 413 "boot_a_script=" \ 414 "load ${devtype} ${devnum}:${distro_bootpart} " \ 415 "${scriptaddr} ${prefix}${script}; " \ 416 "env exists secureboot && load ${devtype} " \ 417 "${devnum}:${distro_bootpart} " \ 418 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 419 "&& esbc_validate ${scripthdraddr};" \ 420 "source ${scriptaddr}\0" \ 421 "qspi_bootcmd=echo Trying load from qspi..;" \ 422 "sf probe && sf read $load_addr " \ 423 "$kernel_start $kernel_size ; env exists secureboot &&" \ 424 "sf read $kernelheader_addr_r $kernelheader_start " \ 425 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 426 " bootm $load_addr#$board\0" \ 427 "nor_bootcmd=echo Trying load from nor..;" \ 428 "cp.b $kernel_addr $load_addr " \ 429 "$kernel_size ; env exists secureboot && " \ 430 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 431 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 432 "bootm $load_addr#$board\0" 433 434 #undef CONFIG_BOOTCOMMAND 435 #ifdef CONFIG_QSPI_BOOT 436 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 437 #define CONFIG_BOOTCOMMAND \ 438 "env exists mcinitcmd && env exists secureboot "\ 439 "&& esbc_validate 0x20780000; " \ 440 "env exists mcinitcmd && " \ 441 "fsl_mc lazyapply dpl 0x20d00000; " \ 442 "run distro_bootcmd;run qspi_bootcmd; " \ 443 "env exists secureboot && esbc_halt;" 444 #elif defined(CONFIG_SD_BOOT) 445 /* Try to boot an on-SD kernel first, then do normal distro boot */ 446 #define CONFIG_BOOTCOMMAND \ 447 "env exists mcinitcmd && env exists secureboot "\ 448 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ 449 "&& esbc_validate $load_addr; " \ 450 "env exists mcinitcmd && run mcinitcmd " \ 451 "&& mmc read 0x88000000 0x6800 0x800 " \ 452 "&& fsl_mc lazyapply dpl 0x88000000; " \ 453 "run distro_bootcmd;run sd_bootcmd; " \ 454 "env exists secureboot && esbc_halt;" 455 #else 456 /* Try to boot an on-NOR kernel first, then do normal distro boot */ 457 #define CONFIG_BOOTCOMMAND \ 458 "env exists mcinitcmd && env exists secureboot "\ 459 "&& esbc_validate 0x580780000; env exists mcinitcmd "\ 460 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 461 "run distro_bootcmd;run nor_bootcmd; " \ 462 "env exists secureboot && esbc_halt;" 463 #endif 464 465 /* MAC/PHY configuration */ 466 #ifdef CONFIG_FSL_MC_ENET 467 #define CONFIG_PHYLIB_10G 468 #define CONFIG_PHY_AQUANTIA 469 #define CONFIG_PHY_CORTINA 470 #define CONFIG_SYS_CORTINA_FW_IN_NOR 471 #ifdef CONFIG_QSPI_BOOT 472 #define CONFIG_CORTINA_FW_ADDR 0x20980000 473 #else 474 #define CONFIG_CORTINA_FW_ADDR 0x580980000 475 #endif 476 #define CONFIG_CORTINA_FW_LENGTH 0x40000 477 478 #define CORTINA_PHY_ADDR1 0x10 479 #define CORTINA_PHY_ADDR2 0x11 480 #define CORTINA_PHY_ADDR3 0x12 481 #define CORTINA_PHY_ADDR4 0x13 482 #define AQ_PHY_ADDR1 0x00 483 #define AQ_PHY_ADDR2 0x01 484 #define AQ_PHY_ADDR3 0x02 485 #define AQ_PHY_ADDR4 0x03 486 #define AQR405_IRQ_MASK 0x36 487 488 #define CONFIG_MII 489 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 490 #define CONFIG_PHY_AQUANTIA 491 #endif 492 493 #include <asm/fsl_secure_boot.h> 494 495 #endif /* __LS2_RDB_H */ 496