1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_FSL_QSPI 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #define CONFIG_SYS_I2C_EARLY_INIT 20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 21 #endif 22 23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 24 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 25 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 26 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 27 28 #define CONFIG_DDR_SPD 29 #define CONFIG_DDR_ECC 30 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 32 #define SPD_EEPROM_ADDRESS1 0x51 33 #define SPD_EEPROM_ADDRESS2 0x52 34 #define SPD_EEPROM_ADDRESS3 0x53 35 #define SPD_EEPROM_ADDRESS4 0x54 36 #define SPD_EEPROM_ADDRESS5 0x55 37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 38 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 40 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 41 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 42 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 43 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 44 #endif 45 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 46 47 /* SATA */ 48 #define CONFIG_SCSI_AHCI_PLAT 49 50 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 51 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 52 53 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 54 #define CONFIG_SYS_SCSI_MAX_LUN 1 55 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 56 CONFIG_SYS_SCSI_MAX_LUN) 57 58 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 59 60 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 61 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 62 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 63 64 #define CONFIG_SYS_NOR0_CSPR \ 65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 66 CSPR_PORT_SIZE_16 | \ 67 CSPR_MSEL_NOR | \ 68 CSPR_V) 69 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 71 CSPR_PORT_SIZE_16 | \ 72 CSPR_MSEL_NOR | \ 73 CSPR_V) 74 #define CONFIG_SYS_NOR1_CSPR \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 76 CSPR_PORT_SIZE_16 | \ 77 CSPR_MSEL_NOR | \ 78 CSPR_V) 79 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 81 CSPR_PORT_SIZE_16 | \ 82 CSPR_MSEL_NOR | \ 83 CSPR_V) 84 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 85 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 86 FTIM0_NOR_TEADC(0x5) | \ 87 FTIM0_NOR_TEAHC(0x5)) 88 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 89 FTIM1_NOR_TRAD_NOR(0x1a) |\ 90 FTIM1_NOR_TSEQRAD_NOR(0x13)) 91 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 92 FTIM2_NOR_TCH(0x4) | \ 93 FTIM2_NOR_TWPH(0x0E) | \ 94 FTIM2_NOR_TWP(0x1c)) 95 #define CONFIG_SYS_NOR_FTIM3 0x04000000 96 #define CONFIG_SYS_IFC_CCR 0x01000000 97 98 #ifdef CONFIG_MTD_NOR_FLASH 99 #define CONFIG_SYS_FLASH_QUIET_TEST 100 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 101 102 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 104 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 105 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 106 107 #define CONFIG_SYS_FLASH_EMPTY_INFO 108 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 109 CONFIG_SYS_FLASH_BASE + 0x40000000} 110 #endif 111 112 #define CONFIG_NAND_FSL_IFC 113 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 114 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 115 116 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 117 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 118 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 119 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 120 | CSPR_V) 121 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 122 123 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 124 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 125 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 126 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 127 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 128 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 129 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 130 131 #define CONFIG_SYS_NAND_ONFI_DETECTION 132 133 /* ONFI NAND Flash mode0 Timing Params */ 134 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 135 FTIM0_NAND_TWP(0x18) | \ 136 FTIM0_NAND_TWCHT(0x07) | \ 137 FTIM0_NAND_TWH(0x0a)) 138 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 139 FTIM1_NAND_TWBE(0x39) | \ 140 FTIM1_NAND_TRR(0x0e) | \ 141 FTIM1_NAND_TRP(0x18)) 142 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 143 FTIM2_NAND_TREH(0x0a) | \ 144 FTIM2_NAND_TWHRE(0x1e)) 145 #define CONFIG_SYS_NAND_FTIM3 0x0 146 147 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 149 #define CONFIG_MTD_NAND_VERIFY_WRITE 150 151 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 152 153 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 154 #define QIXIS_LBMAP_SWITCH 0x06 155 #define QIXIS_LBMAP_MASK 0x0f 156 #define QIXIS_LBMAP_SHIFT 0 157 #define QIXIS_LBMAP_DFLTBANK 0x00 158 #define QIXIS_LBMAP_ALTBANK 0x04 159 #define QIXIS_LBMAP_NAND 0x09 160 #define QIXIS_LBMAP_SD 0x00 161 #define QIXIS_LBMAP_QSPI 0x0f 162 #define QIXIS_RST_CTL_RESET 0x31 163 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 164 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 165 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 166 #define QIXIS_RCW_SRC_NAND 0x107 167 #define QIXIS_RCW_SRC_SD 0x40 168 #define QIXIS_RCW_SRC_QSPI 0x62 169 #define QIXIS_RST_FORCE_MEM 0x01 170 171 #define CONFIG_SYS_CSPR3_EXT (0x0) 172 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 173 | CSPR_PORT_SIZE_8 \ 174 | CSPR_MSEL_GPCM \ 175 | CSPR_V) 176 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_GPCM \ 179 | CSPR_V) 180 181 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 182 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 183 /* QIXIS Timing parameters for IFC CS3 */ 184 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 185 FTIM0_GPCM_TEADC(0x0e) | \ 186 FTIM0_GPCM_TEAHC(0x0e)) 187 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 188 FTIM1_GPCM_TRAD(0x3f)) 189 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 190 FTIM2_GPCM_TCH(0xf) | \ 191 FTIM2_GPCM_TWP(0x3E)) 192 #define CONFIG_SYS_CS3_FTIM3 0x0 193 194 #if defined(CONFIG_SPL) 195 #if defined(CONFIG_NAND_BOOT) 196 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 197 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 198 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 199 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 200 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 201 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 202 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 203 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 204 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 205 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 206 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 207 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 208 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 209 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 223 224 #define CONFIG_ENV_OFFSET (896 * 1024) 225 #define CONFIG_ENV_SECT_SIZE 0x20000 226 #define CONFIG_ENV_SIZE 0x2000 227 #define CONFIG_SPL_PAD_TO 0x20000 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 229 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 230 #elif defined(CONFIG_SD_BOOT) 231 #define CONFIG_ENV_OFFSET 0x300000 232 #define CONFIG_SYS_MMC_ENV_DEV 0 233 #define CONFIG_ENV_SIZE 0x20000 234 #endif 235 #else 236 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 237 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 238 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 239 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 240 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 241 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 242 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 243 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 244 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 245 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 246 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 247 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 248 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 249 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 250 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 251 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 252 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 253 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 254 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 255 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 256 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 257 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 258 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 259 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 260 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 261 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 262 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 263 264 #ifndef CONFIG_QSPI_BOOT 265 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 266 #define CONFIG_ENV_SECT_SIZE 0x20000 267 #define CONFIG_ENV_SIZE 0x2000 268 #endif 269 #endif 270 271 /* Debug Server firmware */ 272 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 273 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 274 275 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 276 277 /* 278 * I2C 279 */ 280 #define I2C_MUX_PCA_ADDR 0x77 281 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 282 283 /* I2C bus multiplexer */ 284 #define I2C_MUX_CH_DEFAULT 0x8 285 286 /* SPI */ 287 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 288 #define CONFIG_SPI_FLASH 289 290 #ifdef CONFIG_FSL_DSPI 291 #define CONFIG_SPI_FLASH_STMICRO 292 #define CONFIG_SPI_FLASH_SST 293 #define CONFIG_SPI_FLASH_EON 294 #endif 295 296 #ifdef CONFIG_FSL_QSPI 297 #define CONFIG_SPI_FLASH_SPANSION 298 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 299 #define FSL_QSPI_FLASH_NUM 4 300 #endif 301 /* 302 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 303 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 304 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 305 */ 306 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 307 308 #endif 309 310 /* 311 * MMC 312 */ 313 #ifdef CONFIG_MMC 314 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 315 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 316 #endif 317 318 /* 319 * RTC configuration 320 */ 321 #define RTC 322 #define CONFIG_RTC_DS3231 1 323 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 324 325 /* EEPROM */ 326 #define CONFIG_ID_EEPROM 327 #define CONFIG_SYS_I2C_EEPROM_NXID 328 #define CONFIG_SYS_EEPROM_BUS_NUM 0 329 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 330 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 332 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 333 334 #define CONFIG_FSL_MEMAC 335 336 #ifdef CONFIG_PCI 337 #define CONFIG_PCI_SCAN_SHOW 338 #endif 339 340 /* MMC */ 341 #ifdef CONFIG_MMC 342 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 343 #endif 344 345 /* Initial environment variables */ 346 #undef CONFIG_EXTRA_ENV_SETTINGS 347 #ifdef CONFIG_SECURE_BOOT 348 #define CONFIG_EXTRA_ENV_SETTINGS \ 349 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 350 "loadaddr=0x80100000\0" \ 351 "kernel_addr=0x100000\0" \ 352 "ramdisk_addr=0x800000\0" \ 353 "ramdisk_size=0x2000000\0" \ 354 "fdt_high=0xa0000000\0" \ 355 "initrd_high=0xffffffffffffffff\0" \ 356 "kernel_start=0x581000000\0" \ 357 "kernel_load=0xa0000000\0" \ 358 "kernel_size=0x2800000\0" \ 359 "mcmemsize=0x40000000\0" \ 360 "mcinitcmd=esbc_validate 0x580700000;" \ 361 "esbc_validate 0x580740000;" \ 362 "fsl_mc start mc 0x580a00000" \ 363 " 0x580e00000 \0" 364 #elif defined(CONFIG_SD_BOOT) 365 #define CONFIG_EXTRA_ENV_SETTINGS \ 366 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 367 "loadaddr=0x90100000\0" \ 368 "kernel_addr=0x800\0" \ 369 "ramdisk_addr=0x800000\0" \ 370 "ramdisk_size=0x2000000\0" \ 371 "fdt_high=0xa0000000\0" \ 372 "initrd_high=0xffffffffffffffff\0" \ 373 "kernel_start=0x8000\0" \ 374 "kernel_load=0xa0000000\0" \ 375 "kernel_size=0x14000\0" \ 376 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 377 "mmc read 0x80100000 0x7000 0x800;" \ 378 "fsl_mc start mc 0x80000000 0x80100000\0" \ 379 "mcmemsize=0x70000000 \0" 380 #else 381 #define CONFIG_EXTRA_ENV_SETTINGS \ 382 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 383 "loadaddr=0x80100000\0" \ 384 "kernel_addr=0x100000\0" \ 385 "ramdisk_addr=0x800000\0" \ 386 "ramdisk_size=0x2000000\0" \ 387 "fdt_high=0xa0000000\0" \ 388 "initrd_high=0xffffffffffffffff\0" \ 389 "kernel_start=0x581000000\0" \ 390 "kernel_load=0xa0000000\0" \ 391 "kernel_size=0x2800000\0" \ 392 "mcmemsize=0x40000000\0" \ 393 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 394 " 0x580e00000 \0" 395 #endif /* CONFIG_SECURE_BOOT */ 396 397 398 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 399 #define CONFIG_FSL_MEMAC 400 #define CONFIG_PHYLIB_10G 401 #define CONFIG_PHY_VITESSE 402 #define CONFIG_PHY_REALTEK 403 #define CONFIG_PHY_TERANETICS 404 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 405 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 406 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 407 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 408 409 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 410 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 411 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 412 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 413 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 414 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 415 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 416 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 417 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 418 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 419 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 420 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 421 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 422 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 423 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 424 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 425 426 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 427 428 #endif 429 430 #include <asm/fsl_secure_boot.h> 431 432 #endif /* __LS2_QDS_H */ 433