1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_QDS_H 9 #define __LS2_QDS_H 10 11 #include "ls2080a_common.h" 12 13 #ifndef __ASSEMBLY__ 14 unsigned long get_board_sys_clk(void); 15 unsigned long get_board_ddr_clk(void); 16 #endif 17 18 #ifdef CONFIG_FSL_QSPI 19 #undef CONFIG_CMD_IMLS 20 #define CONFIG_QIXIS_I2C_ACCESS 21 #define CONFIG_SYS_I2C_EARLY_INIT 22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 23 #endif 24 25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 29 30 #define CONFIG_DDR_SPD 31 #define CONFIG_DDR_ECC 32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34 #define SPD_EEPROM_ADDRESS1 0x51 35 #define SPD_EEPROM_ADDRESS2 0x52 36 #define SPD_EEPROM_ADDRESS3 0x53 37 #define SPD_EEPROM_ADDRESS4 0x54 38 #define SPD_EEPROM_ADDRESS5 0x55 39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 46 #endif 47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 48 49 /* SATA */ 50 #define CONFIG_LIBATA 51 #define CONFIG_SCSI_AHCI 52 #define CONFIG_SCSI_AHCI_PLAT 53 #define CONFIG_SCSI 54 55 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 56 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 57 58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 59 #define CONFIG_SYS_SCSI_MAX_LUN 1 60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 61 CONFIG_SYS_SCSI_MAX_LUN) 62 63 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 64 65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 67 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 68 69 #define CONFIG_SYS_NOR0_CSPR \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 71 CSPR_PORT_SIZE_16 | \ 72 CSPR_MSEL_NOR | \ 73 CSPR_V) 74 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 76 CSPR_PORT_SIZE_16 | \ 77 CSPR_MSEL_NOR | \ 78 CSPR_V) 79 #define CONFIG_SYS_NOR1_CSPR \ 80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 81 CSPR_PORT_SIZE_16 | \ 82 CSPR_MSEL_NOR | \ 83 CSPR_V) 84 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 86 CSPR_PORT_SIZE_16 | \ 87 CSPR_MSEL_NOR | \ 88 CSPR_V) 89 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 90 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 91 FTIM0_NOR_TEADC(0x5) | \ 92 FTIM0_NOR_TEAHC(0x5)) 93 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 94 FTIM1_NOR_TRAD_NOR(0x1a) |\ 95 FTIM1_NOR_TSEQRAD_NOR(0x13)) 96 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 97 FTIM2_NOR_TCH(0x4) | \ 98 FTIM2_NOR_TWPH(0x0E) | \ 99 FTIM2_NOR_TWP(0x1c)) 100 #define CONFIG_SYS_NOR_FTIM3 0x04000000 101 #define CONFIG_SYS_IFC_CCR 0x01000000 102 103 #ifdef CONFIG_MTD_NOR_FLASH 104 #define CONFIG_FLASH_CFI_DRIVER 105 #define CONFIG_SYS_FLASH_CFI 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 107 #define CONFIG_SYS_FLASH_QUIET_TEST 108 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 109 110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 114 115 #define CONFIG_SYS_FLASH_EMPTY_INFO 116 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 117 CONFIG_SYS_FLASH_BASE + 0x40000000} 118 #endif 119 120 #define CONFIG_NAND_FSL_IFC 121 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 122 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 123 124 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 125 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 126 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 127 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 128 | CSPR_V) 129 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 130 131 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 132 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 133 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 134 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 135 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 136 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 137 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 138 139 #define CONFIG_SYS_NAND_ONFI_DETECTION 140 141 /* ONFI NAND Flash mode0 Timing Params */ 142 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 143 FTIM0_NAND_TWP(0x18) | \ 144 FTIM0_NAND_TWCHT(0x07) | \ 145 FTIM0_NAND_TWH(0x0a)) 146 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 147 FTIM1_NAND_TWBE(0x39) | \ 148 FTIM1_NAND_TRR(0x0e) | \ 149 FTIM1_NAND_TRP(0x18)) 150 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 151 FTIM2_NAND_TREH(0x0a) | \ 152 FTIM2_NAND_TWHRE(0x1e)) 153 #define CONFIG_SYS_NAND_FTIM3 0x0 154 155 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 156 #define CONFIG_SYS_MAX_NAND_DEVICE 1 157 #define CONFIG_MTD_NAND_VERIFY_WRITE 158 #define CONFIG_CMD_NAND 159 160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 161 162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 163 #define QIXIS_LBMAP_SWITCH 0x06 164 #define QIXIS_LBMAP_MASK 0x0f 165 #define QIXIS_LBMAP_SHIFT 0 166 #define QIXIS_LBMAP_DFLTBANK 0x00 167 #define QIXIS_LBMAP_ALTBANK 0x04 168 #define QIXIS_LBMAP_NAND 0x09 169 #define QIXIS_LBMAP_QSPI 0x0f 170 #define QIXIS_RST_CTL_RESET 0x31 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 174 #define QIXIS_RCW_SRC_NAND 0x107 175 #define QIXIS_RCW_SRC_QSPI 0x62 176 #define QIXIS_RST_FORCE_MEM 0x01 177 178 #define CONFIG_SYS_CSPR3_EXT (0x0) 179 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 180 | CSPR_PORT_SIZE_8 \ 181 | CSPR_MSEL_GPCM \ 182 | CSPR_V) 183 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 184 | CSPR_PORT_SIZE_8 \ 185 | CSPR_MSEL_GPCM \ 186 | CSPR_V) 187 188 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 189 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 190 /* QIXIS Timing parameters for IFC CS3 */ 191 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 192 FTIM0_GPCM_TEADC(0x0e) | \ 193 FTIM0_GPCM_TEAHC(0x0e)) 194 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 195 FTIM1_GPCM_TRAD(0x3f)) 196 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 197 FTIM2_GPCM_TCH(0xf) | \ 198 FTIM2_GPCM_TWP(0x3E)) 199 #define CONFIG_SYS_CS3_FTIM3 0x0 200 201 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 202 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 203 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 204 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 205 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 206 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 207 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 208 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 209 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 210 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 211 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 212 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 213 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 214 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 215 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 216 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 217 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 218 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 219 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 220 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 221 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 225 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 226 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 227 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 228 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 229 230 #define CONFIG_ENV_IS_IN_NAND 231 #define CONFIG_ENV_OFFSET (896 * 1024) 232 #define CONFIG_ENV_SECT_SIZE 0x20000 233 #define CONFIG_ENV_SIZE 0x2000 234 #define CONFIG_SPL_PAD_TO 0x20000 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 237 #else 238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 240 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 249 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 251 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 252 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 253 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 254 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 255 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 256 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 257 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 258 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 259 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 260 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 261 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 262 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 265 266 #ifndef CONFIG_QSPI_BOOT 267 #define CONFIG_ENV_IS_IN_FLASH 268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 269 #define CONFIG_ENV_SECT_SIZE 0x20000 270 #define CONFIG_ENV_SIZE 0x2000 271 #endif 272 #endif 273 274 /* Debug Server firmware */ 275 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 276 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 277 278 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 279 280 /* 281 * I2C 282 */ 283 #define I2C_MUX_PCA_ADDR 0x77 284 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 285 286 /* I2C bus multiplexer */ 287 #define I2C_MUX_CH_DEFAULT 0x8 288 289 /* SPI */ 290 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 291 #define CONFIG_SPI_FLASH 292 293 #ifdef CONFIG_FSL_DSPI 294 #define CONFIG_SPI_FLASH_STMICRO 295 #define CONFIG_SPI_FLASH_SST 296 #define CONFIG_SPI_FLASH_EON 297 #endif 298 299 #ifdef CONFIG_FSL_QSPI 300 #define CONFIG_SPI_FLASH_SPANSION 301 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 302 #define FSL_QSPI_FLASH_NUM 4 303 #endif 304 /* 305 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 306 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 307 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 308 */ 309 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 310 311 #endif 312 313 /* 314 * MMC 315 */ 316 #ifdef CONFIG_MMC 317 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 318 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 319 #endif 320 321 /* 322 * RTC configuration 323 */ 324 #define RTC 325 #define CONFIG_RTC_DS3231 1 326 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 327 328 /* EEPROM */ 329 #define CONFIG_ID_EEPROM 330 #define CONFIG_SYS_I2C_EEPROM_NXID 331 #define CONFIG_SYS_EEPROM_BUS_NUM 0 332 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 334 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 336 337 #define CONFIG_FSL_MEMAC 338 339 #ifdef CONFIG_PCI 340 #define CONFIG_PCI_SCAN_SHOW 341 #define CONFIG_CMD_PCI 342 #endif 343 344 /* MMC */ 345 #ifdef CONFIG_MMC 346 #define CONFIG_FSL_ESDHC 347 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 348 #endif 349 350 /* Initial environment variables */ 351 #undef CONFIG_EXTRA_ENV_SETTINGS 352 #ifdef CONFIG_SECURE_BOOT 353 #define CONFIG_EXTRA_ENV_SETTINGS \ 354 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 355 "loadaddr=0x80100000\0" \ 356 "kernel_addr=0x100000\0" \ 357 "ramdisk_addr=0x800000\0" \ 358 "ramdisk_size=0x2000000\0" \ 359 "fdt_high=0xa0000000\0" \ 360 "initrd_high=0xffffffffffffffff\0" \ 361 "kernel_start=0x581000000\0" \ 362 "kernel_load=0xa0000000\0" \ 363 "kernel_size=0x2800000\0" \ 364 "mcmemsize=0x40000000\0" \ 365 "mcinitcmd=esbc_validate 0x580700000;" \ 366 "esbc_validate 0x580740000;" \ 367 "fsl_mc start mc 0x580a00000" \ 368 " 0x580e00000 \0" 369 #else 370 #define CONFIG_EXTRA_ENV_SETTINGS \ 371 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 372 "loadaddr=0x80100000\0" \ 373 "kernel_addr=0x100000\0" \ 374 "ramdisk_addr=0x800000\0" \ 375 "ramdisk_size=0x2000000\0" \ 376 "fdt_high=0xa0000000\0" \ 377 "initrd_high=0xffffffffffffffff\0" \ 378 "kernel_start=0x581000000\0" \ 379 "kernel_load=0xa0000000\0" \ 380 "kernel_size=0x2800000\0" \ 381 "mcmemsize=0x40000000\0" \ 382 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 383 " 0x580e00000 \0" 384 #endif /* CONFIG_SECURE_BOOT */ 385 386 387 #ifdef CONFIG_FSL_MC_ENET 388 #define CONFIG_FSL_MEMAC 389 #define CONFIG_PHYLIB 390 #define CONFIG_PHYLIB_10G 391 #define CONFIG_PHY_VITESSE 392 #define CONFIG_PHY_REALTEK 393 #define CONFIG_PHY_TERANETICS 394 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 395 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 396 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 397 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 398 399 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 400 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 401 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 402 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 403 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 404 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 405 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 406 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 407 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 408 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 409 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 410 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 411 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 412 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 413 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 414 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 415 416 #define CONFIG_MII /* MII PHY management */ 417 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 418 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 419 420 #endif 421 422 /* 423 * USB 424 */ 425 #define CONFIG_HAS_FSL_XHCI_USB 426 #define CONFIG_USB_XHCI_FSL 427 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 428 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 429 430 #include <asm/fsl_secure_boot.h> 431 432 #endif /* __LS2_QDS_H */ 433