1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_QDS_H 9 #define __LS2_QDS_H 10 11 #include "ls2080a_common.h" 12 13 #ifndef __ASSEMBLY__ 14 unsigned long get_board_sys_clk(void); 15 unsigned long get_board_ddr_clk(void); 16 #endif 17 18 #ifdef CONFIG_FSL_QSPI 19 #undef CONFIG_CMD_IMLS 20 #define CONFIG_QIXIS_I2C_ACCESS 21 #define CONFIG_SYS_I2C_EARLY_INIT 22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 23 #endif 24 25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 29 30 #define CONFIG_DDR_SPD 31 #define CONFIG_DDR_ECC 32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34 #define SPD_EEPROM_ADDRESS1 0x51 35 #define SPD_EEPROM_ADDRESS2 0x52 36 #define SPD_EEPROM_ADDRESS3 0x53 37 #define SPD_EEPROM_ADDRESS4 0x54 38 #define SPD_EEPROM_ADDRESS5 0x55 39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 46 #endif 47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 48 49 /* SATA */ 50 #define CONFIG_LIBATA 51 #define CONFIG_SCSI_AHCI 52 #define CONFIG_SCSI_AHCI_PLAT 53 54 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 55 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 56 57 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 58 #define CONFIG_SYS_SCSI_MAX_LUN 1 59 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 60 CONFIG_SYS_SCSI_MAX_LUN) 61 62 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 63 64 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 65 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 66 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 67 68 #define CONFIG_SYS_NOR0_CSPR \ 69 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 70 CSPR_PORT_SIZE_16 | \ 71 CSPR_MSEL_NOR | \ 72 CSPR_V) 73 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 75 CSPR_PORT_SIZE_16 | \ 76 CSPR_MSEL_NOR | \ 77 CSPR_V) 78 #define CONFIG_SYS_NOR1_CSPR \ 79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 80 CSPR_PORT_SIZE_16 | \ 81 CSPR_MSEL_NOR | \ 82 CSPR_V) 83 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 84 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 85 CSPR_PORT_SIZE_16 | \ 86 CSPR_MSEL_NOR | \ 87 CSPR_V) 88 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 89 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 90 FTIM0_NOR_TEADC(0x5) | \ 91 FTIM0_NOR_TEAHC(0x5)) 92 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 93 FTIM1_NOR_TRAD_NOR(0x1a) |\ 94 FTIM1_NOR_TSEQRAD_NOR(0x13)) 95 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 96 FTIM2_NOR_TCH(0x4) | \ 97 FTIM2_NOR_TWPH(0x0E) | \ 98 FTIM2_NOR_TWP(0x1c)) 99 #define CONFIG_SYS_NOR_FTIM3 0x04000000 100 #define CONFIG_SYS_IFC_CCR 0x01000000 101 102 #ifdef CONFIG_MTD_NOR_FLASH 103 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 106 #define CONFIG_SYS_FLASH_QUIET_TEST 107 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 108 109 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 111 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 113 114 #define CONFIG_SYS_FLASH_EMPTY_INFO 115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 116 CONFIG_SYS_FLASH_BASE + 0x40000000} 117 #endif 118 119 #define CONFIG_NAND_FSL_IFC 120 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 121 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 122 123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_V) 128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 138 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 140 /* ONFI NAND Flash mode0 Timing Params */ 141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWH(0x0a)) 145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRP(0x18)) 149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TWHRE(0x1e)) 152 #define CONFIG_SYS_NAND_FTIM3 0x0 153 154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 #define CONFIG_CMD_NAND 158 159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 160 161 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 162 #define QIXIS_LBMAP_SWITCH 0x06 163 #define QIXIS_LBMAP_MASK 0x0f 164 #define QIXIS_LBMAP_SHIFT 0 165 #define QIXIS_LBMAP_DFLTBANK 0x00 166 #define QIXIS_LBMAP_ALTBANK 0x04 167 #define QIXIS_LBMAP_NAND 0x09 168 #define QIXIS_LBMAP_SD 0x00 169 #define QIXIS_LBMAP_QSPI 0x0f 170 #define QIXIS_RST_CTL_RESET 0x31 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 174 #define QIXIS_RCW_SRC_NAND 0x107 175 #define QIXIS_RCW_SRC_SD 0x40 176 #define QIXIS_RCW_SRC_QSPI 0x62 177 #define QIXIS_RST_FORCE_MEM 0x01 178 179 #define CONFIG_SYS_CSPR3_EXT (0x0) 180 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 181 | CSPR_PORT_SIZE_8 \ 182 | CSPR_MSEL_GPCM \ 183 | CSPR_V) 184 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 185 | CSPR_PORT_SIZE_8 \ 186 | CSPR_MSEL_GPCM \ 187 | CSPR_V) 188 189 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 190 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 191 /* QIXIS Timing parameters for IFC CS3 */ 192 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 193 FTIM0_GPCM_TEADC(0x0e) | \ 194 FTIM0_GPCM_TEAHC(0x0e)) 195 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 196 FTIM1_GPCM_TRAD(0x3f)) 197 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 198 FTIM2_GPCM_TCH(0xf) | \ 199 FTIM2_GPCM_TWP(0x3E)) 200 #define CONFIG_SYS_CS3_FTIM3 0x0 201 202 #if defined(CONFIG_SPL) 203 #if defined(CONFIG_NAND_BOOT) 204 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 205 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 206 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 207 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 208 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 209 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 210 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 211 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 212 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 213 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 214 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 215 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 216 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 217 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 218 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 219 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 220 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 221 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 222 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 223 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 224 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 225 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 226 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 227 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 228 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 229 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 230 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 231 232 #define CONFIG_ENV_IS_IN_NAND 233 #define CONFIG_ENV_OFFSET (896 * 1024) 234 #define CONFIG_ENV_SECT_SIZE 0x20000 235 #define CONFIG_ENV_SIZE 0x2000 236 #define CONFIG_SPL_PAD_TO 0x20000 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 238 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 239 #elif defined(CONFIG_SD_BOOT) 240 #define CONFIG_ENV_OFFSET 0x200000 241 #define CONFIG_ENV_IS_IN_MMC 242 #define CONFIG_SYS_MMC_ENV_DEV 0 243 #define CONFIG_ENV_SIZE 0x20000 244 #endif 245 #else 246 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 247 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 248 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 255 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 257 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 258 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 259 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 260 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 261 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 262 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 263 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 264 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 265 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 266 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 267 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 268 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 269 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 270 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 271 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 272 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 273 274 #ifndef CONFIG_QSPI_BOOT 275 #define CONFIG_ENV_IS_IN_FLASH 276 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 277 #define CONFIG_ENV_SECT_SIZE 0x20000 278 #define CONFIG_ENV_SIZE 0x2000 279 #endif 280 #endif 281 282 /* Debug Server firmware */ 283 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 284 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 285 286 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 287 288 /* 289 * I2C 290 */ 291 #define I2C_MUX_PCA_ADDR 0x77 292 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 293 294 /* I2C bus multiplexer */ 295 #define I2C_MUX_CH_DEFAULT 0x8 296 297 /* SPI */ 298 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 299 #define CONFIG_SPI_FLASH 300 301 #ifdef CONFIG_FSL_DSPI 302 #define CONFIG_SPI_FLASH_STMICRO 303 #define CONFIG_SPI_FLASH_SST 304 #define CONFIG_SPI_FLASH_EON 305 #endif 306 307 #ifdef CONFIG_FSL_QSPI 308 #define CONFIG_SPI_FLASH_SPANSION 309 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 310 #define FSL_QSPI_FLASH_NUM 4 311 #endif 312 /* 313 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 314 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 315 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 316 */ 317 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 318 319 #endif 320 321 /* 322 * MMC 323 */ 324 #ifdef CONFIG_MMC 325 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 326 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 327 #endif 328 329 /* 330 * RTC configuration 331 */ 332 #define RTC 333 #define CONFIG_RTC_DS3231 1 334 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 335 336 /* EEPROM */ 337 #define CONFIG_ID_EEPROM 338 #define CONFIG_SYS_I2C_EEPROM_NXID 339 #define CONFIG_SYS_EEPROM_BUS_NUM 0 340 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 341 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 342 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 343 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 344 345 #define CONFIG_FSL_MEMAC 346 347 #ifdef CONFIG_PCI 348 #define CONFIG_PCI_SCAN_SHOW 349 #define CONFIG_CMD_PCI 350 #endif 351 352 /* MMC */ 353 #ifdef CONFIG_MMC 354 #define CONFIG_FSL_ESDHC 355 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 356 #endif 357 358 /* Initial environment variables */ 359 #undef CONFIG_EXTRA_ENV_SETTINGS 360 #ifdef CONFIG_SECURE_BOOT 361 #define CONFIG_EXTRA_ENV_SETTINGS \ 362 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 363 "loadaddr=0x80100000\0" \ 364 "kernel_addr=0x100000\0" \ 365 "ramdisk_addr=0x800000\0" \ 366 "ramdisk_size=0x2000000\0" \ 367 "fdt_high=0xa0000000\0" \ 368 "initrd_high=0xffffffffffffffff\0" \ 369 "kernel_start=0x581000000\0" \ 370 "kernel_load=0xa0000000\0" \ 371 "kernel_size=0x2800000\0" \ 372 "mcmemsize=0x40000000\0" \ 373 "mcinitcmd=esbc_validate 0x580700000;" \ 374 "esbc_validate 0x580740000;" \ 375 "fsl_mc start mc 0x580a00000" \ 376 " 0x580e00000 \0" 377 #elif defined(CONFIG_SD_BOOT) 378 #define CONFIG_EXTRA_ENV_SETTINGS \ 379 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 380 "loadaddr=0x90100000\0" \ 381 "kernel_addr=0x800\0" \ 382 "ramdisk_addr=0x800000\0" \ 383 "ramdisk_size=0x2000000\0" \ 384 "fdt_high=0xa0000000\0" \ 385 "initrd_high=0xffffffffffffffff\0" \ 386 "kernel_start=0x8000\0" \ 387 "kernel_load=0xa0000000\0" \ 388 "kernel_size=0x14000\0" \ 389 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 390 "mmc read 0x80100000 0x7000 0x800;" \ 391 "fsl_mc start mc 0x80000000 0x80100000\0" \ 392 "mcmemsize=0x70000000 \0" 393 #else 394 #define CONFIG_EXTRA_ENV_SETTINGS \ 395 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 396 "loadaddr=0x80100000\0" \ 397 "kernel_addr=0x100000\0" \ 398 "ramdisk_addr=0x800000\0" \ 399 "ramdisk_size=0x2000000\0" \ 400 "fdt_high=0xa0000000\0" \ 401 "initrd_high=0xffffffffffffffff\0" \ 402 "kernel_start=0x581000000\0" \ 403 "kernel_load=0xa0000000\0" \ 404 "kernel_size=0x2800000\0" \ 405 "mcmemsize=0x40000000\0" \ 406 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 407 " 0x580e00000 \0" 408 #endif /* CONFIG_SECURE_BOOT */ 409 410 411 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 412 #define CONFIG_FSL_MEMAC 413 #define CONFIG_PHYLIB 414 #define CONFIG_PHYLIB_10G 415 #define CONFIG_PHY_VITESSE 416 #define CONFIG_PHY_REALTEK 417 #define CONFIG_PHY_TERANETICS 418 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 419 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 420 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 421 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 422 423 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 424 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 425 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 426 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 427 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 428 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 429 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 430 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 431 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 432 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 433 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 434 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 435 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 436 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 437 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 438 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 439 440 #define CONFIG_MII /* MII PHY management */ 441 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 442 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 443 444 #endif 445 446 /* 447 * USB 448 */ 449 #define CONFIG_HAS_FSL_XHCI_USB 450 #define CONFIG_USB_XHCI_FSL 451 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 452 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 453 454 #include <asm/fsl_secure_boot.h> 455 456 #endif /* __LS2_QDS_H */ 457