1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 #ifndef __ASSEMBLY__ 15 unsigned long get_board_sys_clk(void); 16 unsigned long get_board_ddr_clk(void); 17 #endif 18 19 #define CONFIG_SYS_FSL_CLK 20 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 21 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 22 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 23 24 #define CONFIG_DDR_SPD 25 #define CONFIG_DDR_ECC 26 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 27 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 28 #define SPD_EEPROM_ADDRESS1 0x51 29 #define SPD_EEPROM_ADDRESS2 0x52 30 #define SPD_EEPROM_ADDRESS3 0x53 31 #define SPD_EEPROM_ADDRESS4 0x54 32 #define SPD_EEPROM_ADDRESS5 0x55 33 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 34 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 35 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 36 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 38 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 39 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 40 #endif 41 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 42 43 /* SATA */ 44 #define CONFIG_LIBATA 45 #define CONFIG_SCSI_AHCI 46 #define CONFIG_SCSI_AHCI_PLAT 47 #define CONFIG_SCSI 48 #define CONFIG_DOS_PARTITION 49 #define CONFIG_BOARD_LATE_INIT 50 51 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 52 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 53 54 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 55 #define CONFIG_SYS_SCSI_MAX_LUN 1 56 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 57 CONFIG_SYS_SCSI_MAX_LUN) 58 59 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 60 61 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 62 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 63 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 64 65 #define CONFIG_SYS_NOR0_CSPR \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 67 CSPR_PORT_SIZE_16 | \ 68 CSPR_MSEL_NOR | \ 69 CSPR_V) 70 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 72 CSPR_PORT_SIZE_16 | \ 73 CSPR_MSEL_NOR | \ 74 CSPR_V) 75 #define CONFIG_SYS_NOR1_CSPR \ 76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 77 CSPR_PORT_SIZE_16 | \ 78 CSPR_MSEL_NOR | \ 79 CSPR_V) 80 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 86 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 87 FTIM0_NOR_TEADC(0x5) | \ 88 FTIM0_NOR_TEAHC(0x5)) 89 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 90 FTIM1_NOR_TRAD_NOR(0x1a) |\ 91 FTIM1_NOR_TSEQRAD_NOR(0x13)) 92 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 93 FTIM2_NOR_TCH(0x4) | \ 94 FTIM2_NOR_TWPH(0x0E) | \ 95 FTIM2_NOR_TWP(0x1c)) 96 #define CONFIG_SYS_NOR_FTIM3 0x04000000 97 #define CONFIG_SYS_IFC_CCR 0x01000000 98 99 #ifndef CONFIG_SYS_NO_FLASH 100 #define CONFIG_FLASH_CFI_DRIVER 101 #define CONFIG_SYS_FLASH_CFI 102 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 103 #define CONFIG_SYS_FLASH_QUIET_TEST 104 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 105 106 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 107 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 108 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 109 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 110 111 #define CONFIG_SYS_FLASH_EMPTY_INFO 112 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 113 CONFIG_SYS_FLASH_BASE + 0x40000000} 114 #endif 115 116 #define CONFIG_NAND_FSL_IFC 117 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 118 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 119 120 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 121 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 122 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 123 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 124 | CSPR_V) 125 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 126 127 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 128 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 129 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 130 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 131 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 132 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 133 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 134 135 #define CONFIG_SYS_NAND_ONFI_DETECTION 136 137 /* ONFI NAND Flash mode0 Timing Params */ 138 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 139 FTIM0_NAND_TWP(0x18) | \ 140 FTIM0_NAND_TWCHT(0x07) | \ 141 FTIM0_NAND_TWH(0x0a)) 142 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 143 FTIM1_NAND_TWBE(0x39) | \ 144 FTIM1_NAND_TRR(0x0e) | \ 145 FTIM1_NAND_TRP(0x18)) 146 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 147 FTIM2_NAND_TREH(0x0a) | \ 148 FTIM2_NAND_TWHRE(0x1e)) 149 #define CONFIG_SYS_NAND_FTIM3 0x0 150 151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_MTD_NAND_VERIFY_WRITE 154 #define CONFIG_CMD_NAND 155 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 157 158 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 159 #define QIXIS_LBMAP_SWITCH 0x06 160 #define QIXIS_LBMAP_MASK 0x0f 161 #define QIXIS_LBMAP_SHIFT 0 162 #define QIXIS_LBMAP_DFLTBANK 0x00 163 #define QIXIS_LBMAP_ALTBANK 0x04 164 #define QIXIS_LBMAP_NAND 0x09 165 #define QIXIS_RST_CTL_RESET 0x31 166 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 167 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 168 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 169 #define QIXIS_RCW_SRC_NAND 0x107 170 #define QIXIS_RST_FORCE_MEM 0x01 171 172 #define CONFIG_SYS_CSPR3_EXT (0x0) 173 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 174 | CSPR_PORT_SIZE_8 \ 175 | CSPR_MSEL_GPCM \ 176 | CSPR_V) 177 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 178 | CSPR_PORT_SIZE_8 \ 179 | CSPR_MSEL_GPCM \ 180 | CSPR_V) 181 182 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 183 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 184 /* QIXIS Timing parameters for IFC CS3 */ 185 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 186 FTIM0_GPCM_TEADC(0x0e) | \ 187 FTIM0_GPCM_TEAHC(0x0e)) 188 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 189 FTIM1_GPCM_TRAD(0x3f)) 190 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 191 FTIM2_GPCM_TCH(0xf) | \ 192 FTIM2_GPCM_TWP(0x3E)) 193 #define CONFIG_SYS_CS3_FTIM3 0x0 194 195 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 196 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 197 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 198 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 199 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 200 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 201 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 202 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 203 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 204 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 205 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 206 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 207 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 208 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 209 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 223 224 #define CONFIG_ENV_IS_IN_NAND 225 #define CONFIG_ENV_OFFSET (896 * 1024) 226 #define CONFIG_ENV_SECT_SIZE 0x20000 227 #define CONFIG_ENV_SIZE 0x2000 228 #define CONFIG_SPL_PAD_TO 0x20000 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 230 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 231 #else 232 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 233 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 234 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 241 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 242 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 243 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 244 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 245 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 246 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 247 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 248 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 249 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 250 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 251 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 252 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 253 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 254 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 255 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 256 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 257 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 258 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 259 260 #define CONFIG_ENV_IS_IN_FLASH 261 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 262 #define CONFIG_ENV_SECT_SIZE 0x20000 263 #define CONFIG_ENV_SIZE 0x2000 264 #endif 265 266 /* Debug Server firmware */ 267 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 268 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 269 270 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 271 272 /* 273 * I2C 274 */ 275 #define I2C_MUX_PCA_ADDR 0x77 276 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 277 278 /* I2C bus multiplexer */ 279 #define I2C_MUX_CH_DEFAULT 0x8 280 281 /* SPI */ 282 #ifdef CONFIG_FSL_DSPI 283 #define CONFIG_SPI_FLASH 284 #endif 285 286 /* 287 * MMC 288 */ 289 #ifdef CONFIG_MMC 290 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 291 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 292 #endif 293 294 /* 295 * RTC configuration 296 */ 297 #define RTC 298 #define CONFIG_RTC_DS3231 1 299 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 300 #define CONFIG_CMD_DATE 301 302 /* EEPROM */ 303 #define CONFIG_ID_EEPROM 304 #define CONFIG_CMD_EEPROM 305 #define CONFIG_SYS_I2C_EEPROM_NXID 306 #define CONFIG_SYS_EEPROM_BUS_NUM 0 307 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 308 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 309 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 311 312 #define CONFIG_FSL_MEMAC 313 #define CONFIG_PCI /* Enable PCIE */ 314 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 315 316 #ifdef CONFIG_PCI 317 #define CONFIG_PCI_PNP 318 #define CONFIG_PCI_SCAN_SHOW 319 #define CONFIG_CMD_PCI 320 #endif 321 322 /* MMC */ 323 #define CONFIG_MMC 324 #ifdef CONFIG_MMC 325 #define CONFIG_FSL_ESDHC 326 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 327 #define CONFIG_GENERIC_MMC 328 #define CONFIG_DOS_PARTITION 329 #endif 330 331 /* Initial environment variables */ 332 #undef CONFIG_EXTRA_ENV_SETTINGS 333 #define CONFIG_EXTRA_ENV_SETTINGS \ 334 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 335 "loadaddr=0x80100000\0" \ 336 "kernel_addr=0x100000\0" \ 337 "ramdisk_addr=0x800000\0" \ 338 "ramdisk_size=0x2000000\0" \ 339 "fdt_high=0xa0000000\0" \ 340 "initrd_high=0xffffffffffffffff\0" \ 341 "kernel_start=0x581100000\0" \ 342 "kernel_load=0xa0000000\0" \ 343 "kernel_size=0x2800000\0" \ 344 "mcinitcmd=fsl_mc start mc 0x580300000" \ 345 " 0x580800000 \0" 346 347 #ifdef CONFIG_FSL_MC_ENET 348 #define CONFIG_FSL_MEMAC 349 #define CONFIG_PHYLIB 350 #define CONFIG_PHYLIB_10G 351 #define CONFIG_PHY_VITESSE 352 #define CONFIG_PHY_REALTEK 353 #define CONFIG_PHY_TERANETICS 354 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 355 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 356 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 357 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 358 359 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 360 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 361 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 362 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 363 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 364 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 365 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 366 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 367 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 368 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 369 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 370 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 371 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 372 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 373 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 374 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 375 376 #define CONFIG_MII /* MII PHY management */ 377 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 378 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 379 380 #endif 381 382 /* 383 * USB 384 */ 385 #define CONFIG_HAS_FSL_XHCI_USB 386 #define CONFIG_USB_XHCI 387 #define CONFIG_USB_XHCI_FSL 388 #define CONFIG_USB_XHCI_DWC3 389 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 390 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 391 #define CONFIG_USB_STORAGE 392 393 #include <asm/fsl_secure_boot.h> 394 395 #endif /* __LS2_QDS_H */ 396