1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_QDS_H 9 #define __LS2_QDS_H 10 11 #include "ls2080a_common.h" 12 13 #ifndef __ASSEMBLY__ 14 unsigned long get_board_sys_clk(void); 15 unsigned long get_board_ddr_clk(void); 16 #endif 17 18 #ifdef CONFIG_FSL_QSPI 19 #undef CONFIG_CMD_IMLS 20 #define CONFIG_QIXIS_I2C_ACCESS 21 #define CONFIG_SYS_I2C_EARLY_INIT 22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 23 #endif 24 25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 29 30 #define CONFIG_DDR_SPD 31 #define CONFIG_DDR_ECC 32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34 #define SPD_EEPROM_ADDRESS1 0x51 35 #define SPD_EEPROM_ADDRESS2 0x52 36 #define SPD_EEPROM_ADDRESS3 0x53 37 #define SPD_EEPROM_ADDRESS4 0x54 38 #define SPD_EEPROM_ADDRESS5 0x55 39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 46 #endif 47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 48 49 /* SATA */ 50 #define CONFIG_LIBATA 51 #define CONFIG_SCSI_AHCI 52 #define CONFIG_SCSI_AHCI_PLAT 53 54 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 55 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 56 57 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 58 #define CONFIG_SYS_SCSI_MAX_LUN 1 59 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 60 CONFIG_SYS_SCSI_MAX_LUN) 61 62 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 63 64 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 65 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 66 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 67 68 #define CONFIG_SYS_NOR0_CSPR \ 69 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 70 CSPR_PORT_SIZE_16 | \ 71 CSPR_MSEL_NOR | \ 72 CSPR_V) 73 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 75 CSPR_PORT_SIZE_16 | \ 76 CSPR_MSEL_NOR | \ 77 CSPR_V) 78 #define CONFIG_SYS_NOR1_CSPR \ 79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 80 CSPR_PORT_SIZE_16 | \ 81 CSPR_MSEL_NOR | \ 82 CSPR_V) 83 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 84 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 85 CSPR_PORT_SIZE_16 | \ 86 CSPR_MSEL_NOR | \ 87 CSPR_V) 88 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 89 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 90 FTIM0_NOR_TEADC(0x5) | \ 91 FTIM0_NOR_TEAHC(0x5)) 92 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 93 FTIM1_NOR_TRAD_NOR(0x1a) |\ 94 FTIM1_NOR_TSEQRAD_NOR(0x13)) 95 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 96 FTIM2_NOR_TCH(0x4) | \ 97 FTIM2_NOR_TWPH(0x0E) | \ 98 FTIM2_NOR_TWP(0x1c)) 99 #define CONFIG_SYS_NOR_FTIM3 0x04000000 100 #define CONFIG_SYS_IFC_CCR 0x01000000 101 102 #ifdef CONFIG_MTD_NOR_FLASH 103 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 106 #define CONFIG_SYS_FLASH_QUIET_TEST 107 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 108 109 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 111 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 113 114 #define CONFIG_SYS_FLASH_EMPTY_INFO 115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 116 CONFIG_SYS_FLASH_BASE + 0x40000000} 117 #endif 118 119 #define CONFIG_NAND_FSL_IFC 120 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 121 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 122 123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_V) 128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 138 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 140 /* ONFI NAND Flash mode0 Timing Params */ 141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWH(0x0a)) 145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRP(0x18)) 149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TWHRE(0x1e)) 152 #define CONFIG_SYS_NAND_FTIM3 0x0 153 154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 158 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 159 160 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 161 #define QIXIS_LBMAP_SWITCH 0x06 162 #define QIXIS_LBMAP_MASK 0x0f 163 #define QIXIS_LBMAP_SHIFT 0 164 #define QIXIS_LBMAP_DFLTBANK 0x00 165 #define QIXIS_LBMAP_ALTBANK 0x04 166 #define QIXIS_LBMAP_NAND 0x09 167 #define QIXIS_LBMAP_SD 0x00 168 #define QIXIS_LBMAP_QSPI 0x0f 169 #define QIXIS_RST_CTL_RESET 0x31 170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 171 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 173 #define QIXIS_RCW_SRC_NAND 0x107 174 #define QIXIS_RCW_SRC_SD 0x40 175 #define QIXIS_RCW_SRC_QSPI 0x62 176 #define QIXIS_RST_FORCE_MEM 0x01 177 178 #define CONFIG_SYS_CSPR3_EXT (0x0) 179 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 180 | CSPR_PORT_SIZE_8 \ 181 | CSPR_MSEL_GPCM \ 182 | CSPR_V) 183 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 184 | CSPR_PORT_SIZE_8 \ 185 | CSPR_MSEL_GPCM \ 186 | CSPR_V) 187 188 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 189 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 190 /* QIXIS Timing parameters for IFC CS3 */ 191 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 192 FTIM0_GPCM_TEADC(0x0e) | \ 193 FTIM0_GPCM_TEAHC(0x0e)) 194 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 195 FTIM1_GPCM_TRAD(0x3f)) 196 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 197 FTIM2_GPCM_TCH(0xf) | \ 198 FTIM2_GPCM_TWP(0x3E)) 199 #define CONFIG_SYS_CS3_FTIM3 0x0 200 201 #if defined(CONFIG_SPL) 202 #if defined(CONFIG_NAND_BOOT) 203 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 204 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 205 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 206 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 207 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 208 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 209 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 210 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 211 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 212 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 213 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 214 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 215 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 216 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 217 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 218 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 219 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 220 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 221 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 230 231 #define CONFIG_ENV_OFFSET (896 * 1024) 232 #define CONFIG_ENV_SECT_SIZE 0x20000 233 #define CONFIG_ENV_SIZE 0x2000 234 #define CONFIG_SPL_PAD_TO 0x20000 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 237 #elif defined(CONFIG_SD_BOOT) 238 #define CONFIG_ENV_OFFSET 0x300000 239 #define CONFIG_SYS_MMC_ENV_DEV 0 240 #define CONFIG_ENV_SIZE 0x20000 241 #endif 242 #else 243 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 244 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 245 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 246 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 247 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 248 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 249 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 250 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 251 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 252 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 253 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 254 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 255 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 256 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 257 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 258 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 259 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 260 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 261 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 262 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 263 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 264 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 265 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 266 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 267 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 268 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 269 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 270 271 #ifndef CONFIG_QSPI_BOOT 272 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 273 #define CONFIG_ENV_SECT_SIZE 0x20000 274 #define CONFIG_ENV_SIZE 0x2000 275 #endif 276 #endif 277 278 /* Debug Server firmware */ 279 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 280 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 281 282 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 283 284 /* 285 * I2C 286 */ 287 #define I2C_MUX_PCA_ADDR 0x77 288 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 289 290 /* I2C bus multiplexer */ 291 #define I2C_MUX_CH_DEFAULT 0x8 292 293 /* SPI */ 294 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 295 #define CONFIG_SPI_FLASH 296 297 #ifdef CONFIG_FSL_DSPI 298 #define CONFIG_SPI_FLASH_STMICRO 299 #define CONFIG_SPI_FLASH_SST 300 #define CONFIG_SPI_FLASH_EON 301 #endif 302 303 #ifdef CONFIG_FSL_QSPI 304 #define CONFIG_SPI_FLASH_SPANSION 305 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 306 #define FSL_QSPI_FLASH_NUM 4 307 #endif 308 /* 309 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 310 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 311 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 312 */ 313 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 314 315 #endif 316 317 /* 318 * MMC 319 */ 320 #ifdef CONFIG_MMC 321 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 322 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 323 #endif 324 325 /* 326 * RTC configuration 327 */ 328 #define RTC 329 #define CONFIG_RTC_DS3231 1 330 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 331 332 /* EEPROM */ 333 #define CONFIG_ID_EEPROM 334 #define CONFIG_SYS_I2C_EEPROM_NXID 335 #define CONFIG_SYS_EEPROM_BUS_NUM 0 336 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 340 341 #define CONFIG_FSL_MEMAC 342 343 #ifdef CONFIG_PCI 344 #define CONFIG_PCI_SCAN_SHOW 345 #endif 346 347 /* MMC */ 348 #ifdef CONFIG_MMC 349 #define CONFIG_FSL_ESDHC 350 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 351 #endif 352 353 /* Initial environment variables */ 354 #undef CONFIG_EXTRA_ENV_SETTINGS 355 #ifdef CONFIG_SECURE_BOOT 356 #define CONFIG_EXTRA_ENV_SETTINGS \ 357 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 358 "loadaddr=0x80100000\0" \ 359 "kernel_addr=0x100000\0" \ 360 "ramdisk_addr=0x800000\0" \ 361 "ramdisk_size=0x2000000\0" \ 362 "fdt_high=0xa0000000\0" \ 363 "initrd_high=0xffffffffffffffff\0" \ 364 "kernel_start=0x581000000\0" \ 365 "kernel_load=0xa0000000\0" \ 366 "kernel_size=0x2800000\0" \ 367 "mcmemsize=0x40000000\0" \ 368 "mcinitcmd=esbc_validate 0x580700000;" \ 369 "esbc_validate 0x580740000;" \ 370 "fsl_mc start mc 0x580a00000" \ 371 " 0x580e00000 \0" 372 #elif defined(CONFIG_SD_BOOT) 373 #define CONFIG_EXTRA_ENV_SETTINGS \ 374 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 375 "loadaddr=0x90100000\0" \ 376 "kernel_addr=0x800\0" \ 377 "ramdisk_addr=0x800000\0" \ 378 "ramdisk_size=0x2000000\0" \ 379 "fdt_high=0xa0000000\0" \ 380 "initrd_high=0xffffffffffffffff\0" \ 381 "kernel_start=0x8000\0" \ 382 "kernel_load=0xa0000000\0" \ 383 "kernel_size=0x14000\0" \ 384 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 385 "mmc read 0x80100000 0x7000 0x800;" \ 386 "fsl_mc start mc 0x80000000 0x80100000\0" \ 387 "mcmemsize=0x70000000 \0" 388 #else 389 #define CONFIG_EXTRA_ENV_SETTINGS \ 390 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 391 "loadaddr=0x80100000\0" \ 392 "kernel_addr=0x100000\0" \ 393 "ramdisk_addr=0x800000\0" \ 394 "ramdisk_size=0x2000000\0" \ 395 "fdt_high=0xa0000000\0" \ 396 "initrd_high=0xffffffffffffffff\0" \ 397 "kernel_start=0x581000000\0" \ 398 "kernel_load=0xa0000000\0" \ 399 "kernel_size=0x2800000\0" \ 400 "mcmemsize=0x40000000\0" \ 401 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 402 " 0x580e00000 \0" 403 #endif /* CONFIG_SECURE_BOOT */ 404 405 406 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 407 #define CONFIG_FSL_MEMAC 408 #define CONFIG_PHYLIB_10G 409 #define CONFIG_PHY_VITESSE 410 #define CONFIG_PHY_REALTEK 411 #define CONFIG_PHY_TERANETICS 412 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 413 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 414 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 415 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 416 417 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 418 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 419 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 420 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 421 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 422 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 423 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 424 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 425 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 426 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 427 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 428 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 429 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 430 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 431 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 432 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 433 434 #define CONFIG_MII /* MII PHY management */ 435 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 436 437 #endif 438 439 /* 440 * USB 441 */ 442 #define CONFIG_HAS_FSL_XHCI_USB 443 #define CONFIG_USB_XHCI_FSL 444 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 445 446 #include <asm/fsl_secure_boot.h> 447 448 #endif /* __LS2_QDS_H */ 449