1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_FSL_QSPI 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #define CONFIG_SYS_I2C_EARLY_INIT 20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 21 #endif 22 23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 24 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 25 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 26 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 27 28 #define CONFIG_DDR_SPD 29 #define CONFIG_DDR_ECC 30 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 32 #define SPD_EEPROM_ADDRESS1 0x51 33 #define SPD_EEPROM_ADDRESS2 0x52 34 #define SPD_EEPROM_ADDRESS3 0x53 35 #define SPD_EEPROM_ADDRESS4 0x54 36 #define SPD_EEPROM_ADDRESS5 0x55 37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 38 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 40 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 41 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 42 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 43 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 44 #endif 45 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 46 47 /* SATA */ 48 #define CONFIG_SCSI_AHCI_PLAT 49 50 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 51 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 52 53 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 54 #define CONFIG_SYS_SCSI_MAX_LUN 1 55 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 56 CONFIG_SYS_SCSI_MAX_LUN) 57 58 #ifdef CONFIG_TFABOOT 59 #define CONFIG_SYS_MMC_ENV_DEV 0 60 #define CONFIG_ENV_SIZE 0x20000 61 #define CONFIG_ENV_OFFSET 0x500000 62 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 63 CONFIG_ENV_OFFSET) 64 #define CONFIG_ENV_SECT_SIZE 0x20000 65 #endif 66 67 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 68 69 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 70 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 71 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 72 73 #define CONFIG_SYS_NOR0_CSPR \ 74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 75 CSPR_PORT_SIZE_16 | \ 76 CSPR_MSEL_NOR | \ 77 CSPR_V) 78 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 80 CSPR_PORT_SIZE_16 | \ 81 CSPR_MSEL_NOR | \ 82 CSPR_V) 83 #define CONFIG_SYS_NOR1_CSPR \ 84 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 85 CSPR_PORT_SIZE_16 | \ 86 CSPR_MSEL_NOR | \ 87 CSPR_V) 88 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 89 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 90 CSPR_PORT_SIZE_16 | \ 91 CSPR_MSEL_NOR | \ 92 CSPR_V) 93 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 94 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 95 FTIM0_NOR_TEADC(0x5) | \ 96 FTIM0_NOR_TEAHC(0x5)) 97 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 98 FTIM1_NOR_TRAD_NOR(0x1a) |\ 99 FTIM1_NOR_TSEQRAD_NOR(0x13)) 100 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 101 FTIM2_NOR_TCH(0x4) | \ 102 FTIM2_NOR_TWPH(0x0E) | \ 103 FTIM2_NOR_TWP(0x1c)) 104 #define CONFIG_SYS_NOR_FTIM3 0x04000000 105 #define CONFIG_SYS_IFC_CCR 0x01000000 106 107 #ifdef CONFIG_MTD_NOR_FLASH 108 #define CONFIG_SYS_FLASH_QUIET_TEST 109 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 110 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 115 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 118 CONFIG_SYS_FLASH_BASE + 0x40000000} 119 #endif 120 121 #define CONFIG_NAND_FSL_IFC 122 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 123 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 124 125 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 126 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 127 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 128 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 129 | CSPR_V) 130 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 131 132 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 133 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 134 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 135 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 136 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 137 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 138 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 139 140 #define CONFIG_SYS_NAND_ONFI_DETECTION 141 142 /* ONFI NAND Flash mode0 Timing Params */ 143 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 144 FTIM0_NAND_TWP(0x18) | \ 145 FTIM0_NAND_TWCHT(0x07) | \ 146 FTIM0_NAND_TWH(0x0a)) 147 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 148 FTIM1_NAND_TWBE(0x39) | \ 149 FTIM1_NAND_TRR(0x0e) | \ 150 FTIM1_NAND_TRP(0x18)) 151 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 152 FTIM2_NAND_TREH(0x0a) | \ 153 FTIM2_NAND_TWHRE(0x1e)) 154 #define CONFIG_SYS_NAND_FTIM3 0x0 155 156 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 157 #define CONFIG_SYS_MAX_NAND_DEVICE 1 158 #define CONFIG_MTD_NAND_VERIFY_WRITE 159 160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 161 162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 163 #define QIXIS_LBMAP_SWITCH 0x06 164 #define QIXIS_LBMAP_MASK 0x0f 165 #define QIXIS_LBMAP_SHIFT 0 166 #define QIXIS_LBMAP_DFLTBANK 0x00 167 #define QIXIS_LBMAP_ALTBANK 0x04 168 #define QIXIS_LBMAP_NAND 0x09 169 #define QIXIS_LBMAP_SD 0x00 170 #define QIXIS_LBMAP_QSPI 0x0f 171 #define QIXIS_RST_CTL_RESET 0x31 172 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 173 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 174 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 175 #define QIXIS_RCW_SRC_NAND 0x107 176 #define QIXIS_RCW_SRC_SD 0x40 177 #define QIXIS_RCW_SRC_QSPI 0x62 178 #define QIXIS_RST_FORCE_MEM 0x01 179 180 #define CONFIG_SYS_CSPR3_EXT (0x0) 181 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 182 | CSPR_PORT_SIZE_8 \ 183 | CSPR_MSEL_GPCM \ 184 | CSPR_V) 185 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 186 | CSPR_PORT_SIZE_8 \ 187 | CSPR_MSEL_GPCM \ 188 | CSPR_V) 189 190 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 191 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 192 /* QIXIS Timing parameters for IFC CS3 */ 193 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 194 FTIM0_GPCM_TEADC(0x0e) | \ 195 FTIM0_GPCM_TEAHC(0x0e)) 196 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 197 FTIM1_GPCM_TRAD(0x3f)) 198 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 199 FTIM2_GPCM_TCH(0xf) | \ 200 FTIM2_GPCM_TWP(0x3E)) 201 #define CONFIG_SYS_CS3_FTIM3 0x0 202 203 #if defined(CONFIG_SPL) 204 #if defined(CONFIG_NAND_BOOT) 205 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 206 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 207 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 208 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 209 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 210 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 211 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 212 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 213 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 214 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 215 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 216 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 217 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 218 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 219 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 220 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 221 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 222 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 223 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 224 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 225 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 226 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 227 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 228 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 229 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 230 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 231 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 232 233 #define CONFIG_ENV_OFFSET (896 * 1024) 234 #define CONFIG_ENV_SECT_SIZE 0x20000 235 #define CONFIG_ENV_SIZE 0x2000 236 #define CONFIG_SPL_PAD_TO 0x20000 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 238 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 239 #elif defined(CONFIG_SD_BOOT) 240 #define CONFIG_ENV_OFFSET 0x300000 241 #define CONFIG_SYS_MMC_ENV_DEV 0 242 #define CONFIG_ENV_SIZE 0x20000 243 #endif 244 #else 245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 247 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 248 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 249 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 250 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 251 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 252 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 253 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 254 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 255 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 256 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 258 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 264 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 265 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 266 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 267 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 268 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 269 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 270 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 271 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 272 273 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT) 274 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 275 #define CONFIG_ENV_SECT_SIZE 0x20000 276 #define CONFIG_ENV_SIZE 0x2000 277 #endif 278 #endif 279 280 /* Debug Server firmware */ 281 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 282 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 283 284 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 285 286 /* 287 * I2C 288 */ 289 #define I2C_MUX_PCA_ADDR 0x77 290 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 291 292 /* I2C bus multiplexer */ 293 #define I2C_MUX_CH_DEFAULT 0x8 294 295 /* SPI */ 296 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 297 #ifdef CONFIG_FSL_DSPI 298 #define CONFIG_SPI_FLASH_STMICRO 299 #define CONFIG_SPI_FLASH_SST 300 #define CONFIG_SPI_FLASH_EON 301 #endif 302 303 #ifdef CONFIG_FSL_QSPI 304 #define CONFIG_SPI_FLASH_SPANSION 305 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 306 #define FSL_QSPI_FLASH_NUM 4 307 #endif 308 /* 309 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 310 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 311 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 312 */ 313 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 314 315 #endif 316 317 /* 318 * MMC 319 */ 320 #ifdef CONFIG_MMC 321 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 322 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 323 #endif 324 325 /* 326 * RTC configuration 327 */ 328 #define RTC 329 #define CONFIG_RTC_DS3231 1 330 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 331 332 /* EEPROM */ 333 #define CONFIG_ID_EEPROM 334 #define CONFIG_SYS_I2C_EEPROM_NXID 335 #define CONFIG_SYS_EEPROM_BUS_NUM 0 336 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 340 341 #define CONFIG_FSL_MEMAC 342 343 #ifdef CONFIG_PCI 344 #define CONFIG_PCI_SCAN_SHOW 345 #endif 346 347 /* MMC */ 348 #ifdef CONFIG_MMC 349 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 350 #endif 351 352 /* Initial environment variables */ 353 #undef CONFIG_EXTRA_ENV_SETTINGS 354 #ifdef CONFIG_SECURE_BOOT 355 #define CONFIG_EXTRA_ENV_SETTINGS \ 356 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 357 "loadaddr=0x80100000\0" \ 358 "kernel_addr=0x100000\0" \ 359 "ramdisk_addr=0x800000\0" \ 360 "ramdisk_size=0x2000000\0" \ 361 "fdt_high=0xa0000000\0" \ 362 "initrd_high=0xffffffffffffffff\0" \ 363 "kernel_start=0x581000000\0" \ 364 "kernel_load=0xa0000000\0" \ 365 "kernel_size=0x2800000\0" \ 366 "mcmemsize=0x40000000\0" \ 367 "mcinitcmd=esbc_validate 0x580700000;" \ 368 "esbc_validate 0x580740000;" \ 369 "fsl_mc start mc 0x580a00000" \ 370 " 0x580e00000 \0" 371 #else 372 #ifdef CONFIG_TFABOOT 373 #define SD_MC_INIT_CMD \ 374 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 375 "mmc read 0x80100000 0x7000 0x800;" \ 376 "fsl_mc start mc 0x80000000 0x80100000\0" 377 #define IFC_MC_INIT_CMD \ 378 "fsl_mc start mc 0x580a00000" \ 379 " 0x580e00000 \0" 380 #define CONFIG_EXTRA_ENV_SETTINGS \ 381 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 382 "loadaddr=0x80100000\0" \ 383 "loadaddr_sd=0x90100000\0" \ 384 "kernel_addr=0x100000\0" \ 385 "kernel_addr_sd=0x800\0" \ 386 "ramdisk_addr=0x800000\0" \ 387 "ramdisk_size=0x2000000\0" \ 388 "fdt_high=0xa0000000\0" \ 389 "initrd_high=0xffffffffffffffff\0" \ 390 "kernel_start=0x581000000\0" \ 391 "kernel_start_sd=0x8000\0" \ 392 "kernel_load=0xa0000000\0" \ 393 "kernel_size=0x2800000\0" \ 394 "kernel_size_sd=0x14000\0" \ 395 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 396 " 0x580e00000 \0" \ 397 "mcmemsize=0x70000000 \0" 398 #elif defined(CONFIG_SD_BOOT) 399 #define CONFIG_EXTRA_ENV_SETTINGS \ 400 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 401 "loadaddr=0x90100000\0" \ 402 "kernel_addr=0x800\0" \ 403 "ramdisk_addr=0x800000\0" \ 404 "ramdisk_size=0x2000000\0" \ 405 "fdt_high=0xa0000000\0" \ 406 "initrd_high=0xffffffffffffffff\0" \ 407 "kernel_start=0x8000\0" \ 408 "kernel_load=0xa0000000\0" \ 409 "kernel_size=0x14000\0" \ 410 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 411 "mmc read 0x80100000 0x7000 0x800;" \ 412 "fsl_mc start mc 0x80000000 0x80100000\0" \ 413 "mcmemsize=0x70000000 \0" 414 #else 415 #define CONFIG_EXTRA_ENV_SETTINGS \ 416 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 417 "loadaddr=0x80100000\0" \ 418 "kernel_addr=0x100000\0" \ 419 "ramdisk_addr=0x800000\0" \ 420 "ramdisk_size=0x2000000\0" \ 421 "fdt_high=0xa0000000\0" \ 422 "initrd_high=0xffffffffffffffff\0" \ 423 "kernel_start=0x581000000\0" \ 424 "kernel_load=0xa0000000\0" \ 425 "kernel_size=0x2800000\0" \ 426 "mcmemsize=0x40000000\0" \ 427 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 428 " 0x580e00000 \0" 429 #endif /* CONFIG_TFABOOT */ 430 #endif /* CONFIG_SECURE_BOOT */ 431 432 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 433 #define CONFIG_FSL_MEMAC 434 #define CONFIG_PHYLIB_10G 435 #define CONFIG_PHY_VITESSE 436 #define CONFIG_PHY_REALTEK 437 #define CONFIG_PHY_TERANETICS 438 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 439 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 440 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 441 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 442 443 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 444 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 445 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 446 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 447 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 448 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 449 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 450 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 451 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 452 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 453 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 454 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 455 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 456 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 457 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 458 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 459 460 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 461 462 #endif 463 464 #include <asm/fsl_secure_boot.h> 465 466 #endif /* __LS2_QDS_H */ 467