1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 #ifndef __ASSEMBLY__ 15 unsigned long get_board_sys_clk(void); 16 unsigned long get_board_ddr_clk(void); 17 #endif 18 19 #define CONFIG_SYS_FSL_CLK 20 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 21 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 22 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 23 24 #define CONFIG_DDR_SPD 25 #define CONFIG_DDR_ECC 26 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 27 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 28 #define SPD_EEPROM_ADDRESS1 0x51 29 #define SPD_EEPROM_ADDRESS2 0x52 30 #define SPD_EEPROM_ADDRESS3 0x53 31 #define SPD_EEPROM_ADDRESS4 0x54 32 #define SPD_EEPROM_ADDRESS5 0x55 33 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 34 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 35 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 36 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 38 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 39 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 40 #endif 41 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 42 43 /* SATA */ 44 #define CONFIG_LIBATA 45 #define CONFIG_SCSI_AHCI 46 #define CONFIG_SCSI_AHCI_PLAT 47 #define CONFIG_CMD_SCSI 48 #define CONFIG_CMD_FAT 49 #define CONFIG_CMD_EXT2 50 #define CONFIG_DOS_PARTITION 51 #define CONFIG_BOARD_LATE_INIT 52 53 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 54 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 55 56 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 57 #define CONFIG_SYS_SCSI_MAX_LUN 1 58 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 59 CONFIG_SYS_SCSI_MAX_LUN) 60 61 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 62 63 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 65 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 66 67 #define CONFIG_SYS_NOR0_CSPR \ 68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 69 CSPR_PORT_SIZE_16 | \ 70 CSPR_MSEL_NOR | \ 71 CSPR_V) 72 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 74 CSPR_PORT_SIZE_16 | \ 75 CSPR_MSEL_NOR | \ 76 CSPR_V) 77 #define CONFIG_SYS_NOR1_CSPR \ 78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 79 CSPR_PORT_SIZE_16 | \ 80 CSPR_MSEL_NOR | \ 81 CSPR_V) 82 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 84 CSPR_PORT_SIZE_16 | \ 85 CSPR_MSEL_NOR | \ 86 CSPR_V) 87 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 88 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 89 FTIM0_NOR_TEADC(0x5) | \ 90 FTIM0_NOR_TEAHC(0x5)) 91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) |\ 93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 95 FTIM2_NOR_TCH(0x4) | \ 96 FTIM2_NOR_TWPH(0x0E) | \ 97 FTIM2_NOR_TWP(0x1c)) 98 #define CONFIG_SYS_NOR_FTIM3 0x04000000 99 #define CONFIG_SYS_IFC_CCR 0x01000000 100 101 #ifndef CONFIG_SYS_NO_FLASH 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 #define CONFIG_SYS_FLASH_QUIET_TEST 106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 107 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 115 CONFIG_SYS_FLASH_BASE + 0x40000000} 116 #endif 117 118 #define CONFIG_NAND_FSL_IFC 119 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 120 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 121 122 123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_V) 128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 138 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 140 /* ONFI NAND Flash mode0 Timing Params */ 141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWH(0x0a)) 145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRP(0x18)) 149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TWHRE(0x1e)) 152 #define CONFIG_SYS_NAND_FTIM3 0x0 153 154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 #define CONFIG_CMD_NAND 158 159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 160 161 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 162 #define QIXIS_LBMAP_SWITCH 0x06 163 #define QIXIS_LBMAP_MASK 0x0f 164 #define QIXIS_LBMAP_SHIFT 0 165 #define QIXIS_LBMAP_DFLTBANK 0x00 166 #define QIXIS_LBMAP_ALTBANK 0x04 167 #define QIXIS_LBMAP_NAND 0x09 168 #define QIXIS_RST_CTL_RESET 0x31 169 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 170 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 171 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 172 #define QIXIS_RCW_SRC_NAND 0x107 173 #define QIXIS_RST_FORCE_MEM 0x01 174 175 #define CONFIG_SYS_CSPR3_EXT (0x0) 176 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_GPCM \ 179 | CSPR_V) 180 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 181 | CSPR_PORT_SIZE_8 \ 182 | CSPR_MSEL_GPCM \ 183 | CSPR_V) 184 185 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 186 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 187 /* QIXIS Timing parameters for IFC CS3 */ 188 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 189 FTIM0_GPCM_TEADC(0x0e) | \ 190 FTIM0_GPCM_TEAHC(0x0e)) 191 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 192 FTIM1_GPCM_TRAD(0x3f)) 193 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 194 FTIM2_GPCM_TCH(0xf) | \ 195 FTIM2_GPCM_TWP(0x3E)) 196 #define CONFIG_SYS_CS3_FTIM3 0x0 197 198 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 199 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 200 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 201 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 202 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 203 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 204 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 205 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 206 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 207 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 208 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 209 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 210 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 211 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 212 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 213 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 214 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 215 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 216 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 217 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 218 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 226 227 #define CONFIG_ENV_IS_IN_NAND 228 #define CONFIG_ENV_OFFSET (896 * 1024) 229 #define CONFIG_ENV_SECT_SIZE 0x20000 230 #define CONFIG_ENV_SIZE 0x2000 231 #define CONFIG_SPL_PAD_TO 0x20000 232 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 233 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) 234 #else 235 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 236 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 237 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 238 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 239 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 240 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 241 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 242 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 243 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 244 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 245 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 246 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 247 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 248 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 249 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 254 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 255 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 256 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 257 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 258 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 259 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 260 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 261 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 262 263 #define CONFIG_ENV_IS_IN_FLASH 264 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 265 #define CONFIG_ENV_SECT_SIZE 0x20000 266 #define CONFIG_ENV_SIZE 0x2000 267 #endif 268 269 /* Debug Server firmware */ 270 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 271 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 272 273 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 274 275 /* 276 * I2C 277 */ 278 #define I2C_MUX_PCA_ADDR 0x77 279 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 280 281 /* I2C bus multiplexer */ 282 #define I2C_MUX_CH_DEFAULT 0x8 283 284 /* SPI */ 285 #ifdef CONFIG_FSL_DSPI 286 #define CONFIG_CMD_SF 287 #define CONFIG_SPI_FLASH 288 #endif 289 290 /* 291 * MMC 292 */ 293 #ifdef CONFIG_MMC 294 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 295 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 296 #endif 297 298 /* 299 * RTC configuration 300 */ 301 #define RTC 302 #define CONFIG_RTC_DS3231 1 303 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 304 #define CONFIG_CMD_DATE 305 306 /* EEPROM */ 307 #define CONFIG_ID_EEPROM 308 #define CONFIG_CMD_EEPROM 309 #define CONFIG_SYS_I2C_EEPROM_NXID 310 #define CONFIG_SYS_EEPROM_BUS_NUM 0 311 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 312 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 315 316 #define CONFIG_FSL_MEMAC 317 #define CONFIG_PCI /* Enable PCIE */ 318 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 319 320 #ifdef CONFIG_PCI 321 #define CONFIG_PCI_PNP 322 #define CONFIG_PCI_SCAN_SHOW 323 #define CONFIG_CMD_PCI 324 #endif 325 326 /* MMC */ 327 #define CONFIG_MMC 328 #ifdef CONFIG_MMC 329 #define CONFIG_CMD_MMC 330 #define CONFIG_FSL_ESDHC 331 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 332 #define CONFIG_GENERIC_MMC 333 #define CONFIG_CMD_FAT 334 #define CONFIG_DOS_PARTITION 335 #endif 336 337 /* Initial environment variables */ 338 #undef CONFIG_EXTRA_ENV_SETTINGS 339 #define CONFIG_EXTRA_ENV_SETTINGS \ 340 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 341 "loadaddr=0x80100000\0" \ 342 "kernel_addr=0x100000\0" \ 343 "ramdisk_addr=0x800000\0" \ 344 "ramdisk_size=0x2000000\0" \ 345 "fdt_high=0xa0000000\0" \ 346 "initrd_high=0xffffffffffffffff\0" \ 347 "kernel_start=0x581100000\0" \ 348 "kernel_load=0xa0000000\0" \ 349 "kernel_size=0x28000000\0" 350 351 #ifdef CONFIG_FSL_MC_ENET 352 #define CONFIG_FSL_MEMAC 353 #define CONFIG_PHYLIB 354 #define CONFIG_PHYLIB_10G 355 #define CONFIG_CMD_MII 356 #define CONFIG_PHY_VITESSE 357 #define CONFIG_PHY_REALTEK 358 #define CONFIG_PHY_TERANETICS 359 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 360 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 361 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 362 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 363 364 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 365 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 366 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 367 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 368 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 369 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 370 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 371 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 372 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 373 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 374 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 375 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 376 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 377 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 378 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 379 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 380 381 #define CONFIG_MII /* MII PHY management */ 382 #define CONFIG_ETHPRIME "DPNI1" 383 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 384 385 #endif 386 387 /* 388 * USB 389 */ 390 #define CONFIG_HAS_FSL_XHCI_USB 391 #define CONFIG_USB_XHCI 392 #define CONFIG_USB_XHCI_FSL 393 #define CONFIG_USB_XHCI_DWC3 394 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 395 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 396 #define CONFIG_CMD_USB 397 #define CONFIG_USB_STORAGE 398 #define CONFIG_CMD_EXT2 399 400 #endif /* __LS2_QDS_H */ 401