183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 244937214SPrabhakar Kushwaha /* 389a168f7SPriyanka Jain * Copyright 2017 NXP 444937214SPrabhakar Kushwaha * Copyright 2015 Freescale Semiconductor 544937214SPrabhakar Kushwaha */ 644937214SPrabhakar Kushwaha 744937214SPrabhakar Kushwaha #ifndef __LS2_QDS_H 844937214SPrabhakar Kushwaha #define __LS2_QDS_H 944937214SPrabhakar Kushwaha 1044937214SPrabhakar Kushwaha #include "ls2080a_common.h" 1144937214SPrabhakar Kushwaha 1244937214SPrabhakar Kushwaha #ifndef __ASSEMBLY__ 1344937214SPrabhakar Kushwaha unsigned long get_board_sys_clk(void); 1444937214SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void); 1544937214SPrabhakar Kushwaha #endif 1644937214SPrabhakar Kushwaha 178c77ef85SYuan Yao #ifdef CONFIG_FSL_QSPI 188c77ef85SYuan Yao #define CONFIG_QIXIS_I2C_ACCESS 198c77ef85SYuan Yao #define CONFIG_SYS_I2C_EARLY_INIT 208c77ef85SYuan Yao #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 218c77ef85SYuan Yao #endif 228c77ef85SYuan Yao 238c77ef85SYuan Yao #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 2444937214SPrabhakar Kushwaha #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 2544937214SPrabhakar Kushwaha #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 2644937214SPrabhakar Kushwaha #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 2744937214SPrabhakar Kushwaha 2844937214SPrabhakar Kushwaha #define CONFIG_DDR_SPD 2944937214SPrabhakar Kushwaha #define CONFIG_DDR_ECC 3044937214SPrabhakar Kushwaha #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 3144937214SPrabhakar Kushwaha #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 3244937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS1 0x51 3344937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS2 0x52 3444937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS3 0x53 3544937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS4 0x54 3644937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS5 0x55 3744937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 3844937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 3944937214SPrabhakar Kushwaha #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 4044937214SPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 2 4144937214SPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 4 4244937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 4344937214SPrabhakar Kushwaha #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 4444937214SPrabhakar Kushwaha #endif 4544937214SPrabhakar Kushwaha 46989c5f0aSTang Yuantian /* SATA */ 47989c5f0aSTang Yuantian #define CONFIG_SCSI_AHCI_PLAT 48989c5f0aSTang Yuantian 49989c5f0aSTang Yuantian #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 50989c5f0aSTang Yuantian #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 51989c5f0aSTang Yuantian 52989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 53989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_LUN 1 54989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 55989c5f0aSTang Yuantian CONFIG_SYS_SCSI_MAX_LUN) 56989c5f0aSTang Yuantian 57*1908201cSRajesh Bhagat #ifdef CONFIG_TFABOOT 58*1908201cSRajesh Bhagat #define CONFIG_SYS_MMC_ENV_DEV 0 59*1908201cSRajesh Bhagat #define CONFIG_ENV_SIZE 0x20000 60*1908201cSRajesh Bhagat #define CONFIG_ENV_OFFSET 0x500000 61*1908201cSRajesh Bhagat #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 62*1908201cSRajesh Bhagat CONFIG_ENV_OFFSET) 63*1908201cSRajesh Bhagat #define CONFIG_ENV_SECT_SIZE 0x20000 64*1908201cSRajesh Bhagat #endif 65*1908201cSRajesh Bhagat 6644937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 6744937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 6844937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 6944937214SPrabhakar Kushwaha 7044937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR \ 7144937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 7244937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 7344937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 7444937214SPrabhakar Kushwaha CSPR_V) 7544937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EARLY \ 7644937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 7744937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 7844937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 7944937214SPrabhakar Kushwaha CSPR_V) 8044937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR1_CSPR \ 8144937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 8244937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 8344937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 8444937214SPrabhakar Kushwaha CSPR_V) 8544937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR1_CSPR_EARLY \ 8644937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 8744937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 8844937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 8944937214SPrabhakar Kushwaha CSPR_V) 9044937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 9144937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 9244937214SPrabhakar Kushwaha FTIM0_NOR_TEADC(0x5) | \ 9344937214SPrabhakar Kushwaha FTIM0_NOR_TEAHC(0x5)) 9444937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 9544937214SPrabhakar Kushwaha FTIM1_NOR_TRAD_NOR(0x1a) |\ 9644937214SPrabhakar Kushwaha FTIM1_NOR_TSEQRAD_NOR(0x13)) 9744937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 9844937214SPrabhakar Kushwaha FTIM2_NOR_TCH(0x4) | \ 9944937214SPrabhakar Kushwaha FTIM2_NOR_TWPH(0x0E) | \ 10044937214SPrabhakar Kushwaha FTIM2_NOR_TWP(0x1c)) 10144937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM3 0x04000000 10244937214SPrabhakar Kushwaha #define CONFIG_SYS_IFC_CCR 0x01000000 10344937214SPrabhakar Kushwaha 104e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH 10544937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_QUIET_TEST 10644937214SPrabhakar Kushwaha #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 10744937214SPrabhakar Kushwaha 10844937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 10944937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 11044937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 11144937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 11244937214SPrabhakar Kushwaha 11344937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_EMPTY_INFO 11444937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 11544937214SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE + 0x40000000} 11644937214SPrabhakar Kushwaha #endif 11744937214SPrabhakar Kushwaha 11844937214SPrabhakar Kushwaha #define CONFIG_NAND_FSL_IFC 11944937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 256 12044937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 2 12144937214SPrabhakar Kushwaha 12244937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 12344937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 12444937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 12544937214SPrabhakar Kushwaha | CSPR_MSEL_NAND /* MSEL = NAND */ \ 12644937214SPrabhakar Kushwaha | CSPR_V) 12744937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 12844937214SPrabhakar Kushwaha 12944937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 13044937214SPrabhakar Kushwaha | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 13144937214SPrabhakar Kushwaha | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 13244937214SPrabhakar Kushwaha | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 13344937214SPrabhakar Kushwaha | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 13444937214SPrabhakar Kushwaha | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 13544937214SPrabhakar Kushwaha | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 13644937214SPrabhakar Kushwaha 13744937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_ONFI_DETECTION 13844937214SPrabhakar Kushwaha 13944937214SPrabhakar Kushwaha /* ONFI NAND Flash mode0 Timing Params */ 14044937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 14144937214SPrabhakar Kushwaha FTIM0_NAND_TWP(0x18) | \ 14244937214SPrabhakar Kushwaha FTIM0_NAND_TWCHT(0x07) | \ 14344937214SPrabhakar Kushwaha FTIM0_NAND_TWH(0x0a)) 14444937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 14544937214SPrabhakar Kushwaha FTIM1_NAND_TWBE(0x39) | \ 14644937214SPrabhakar Kushwaha FTIM1_NAND_TRR(0x0e) | \ 14744937214SPrabhakar Kushwaha FTIM1_NAND_TRP(0x18)) 14844937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 14944937214SPrabhakar Kushwaha FTIM2_NAND_TREH(0x0a) | \ 15044937214SPrabhakar Kushwaha FTIM2_NAND_TWHRE(0x1e)) 15144937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM3 0x0 15244937214SPrabhakar Kushwaha 15344937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 15444937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_NAND_DEVICE 1 15544937214SPrabhakar Kushwaha #define CONFIG_MTD_NAND_VERIFY_WRITE 15644937214SPrabhakar Kushwaha 15744937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 15844937214SPrabhakar Kushwaha 15944937214SPrabhakar Kushwaha #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 16044937214SPrabhakar Kushwaha #define QIXIS_LBMAP_SWITCH 0x06 16144937214SPrabhakar Kushwaha #define QIXIS_LBMAP_MASK 0x0f 16244937214SPrabhakar Kushwaha #define QIXIS_LBMAP_SHIFT 0 16344937214SPrabhakar Kushwaha #define QIXIS_LBMAP_DFLTBANK 0x00 16444937214SPrabhakar Kushwaha #define QIXIS_LBMAP_ALTBANK 0x04 16544937214SPrabhakar Kushwaha #define QIXIS_LBMAP_NAND 0x09 1661f55a938SSantan Kumar #define QIXIS_LBMAP_SD 0x00 167a646f669SYuan Yao #define QIXIS_LBMAP_QSPI 0x0f 16844937214SPrabhakar Kushwaha #define QIXIS_RST_CTL_RESET 0x31 16944937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 17044937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 17144937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 17244937214SPrabhakar Kushwaha #define QIXIS_RCW_SRC_NAND 0x107 1731f55a938SSantan Kumar #define QIXIS_RCW_SRC_SD 0x40 174a646f669SYuan Yao #define QIXIS_RCW_SRC_QSPI 0x62 17544937214SPrabhakar Kushwaha #define QIXIS_RST_FORCE_MEM 0x01 17644937214SPrabhakar Kushwaha 17744937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3_EXT (0x0) 17844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 17944937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 \ 18044937214SPrabhakar Kushwaha | CSPR_MSEL_GPCM \ 18144937214SPrabhakar Kushwaha | CSPR_V) 18244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 18344937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 \ 18444937214SPrabhakar Kushwaha | CSPR_MSEL_GPCM \ 18544937214SPrabhakar Kushwaha | CSPR_V) 18644937214SPrabhakar Kushwaha 18744937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 18844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 18944937214SPrabhakar Kushwaha /* QIXIS Timing parameters for IFC CS3 */ 19044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 19144937214SPrabhakar Kushwaha FTIM0_GPCM_TEADC(0x0e) | \ 19244937214SPrabhakar Kushwaha FTIM0_GPCM_TEAHC(0x0e)) 19344937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 19444937214SPrabhakar Kushwaha FTIM1_GPCM_TRAD(0x3f)) 19544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 19644937214SPrabhakar Kushwaha FTIM2_GPCM_TCH(0xf) | \ 19744937214SPrabhakar Kushwaha FTIM2_GPCM_TWP(0x3E)) 19844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM3 0x0 19944937214SPrabhakar Kushwaha 200faed6bdeSSantan Kumar #if defined(CONFIG_SPL) 201faed6bdeSSantan Kumar #if defined(CONFIG_NAND_BOOT) 20244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 20344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 20444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 20544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 20644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 20744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 20844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 20944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 21044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 21144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 21244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 21344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 21444937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 21544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 21644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 21744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 21844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 21944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 22044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 22144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 22244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 22344937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 22444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 22544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 22644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 22744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 22844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 22944937214SPrabhakar Kushwaha 23044937214SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET (896 * 1024) 23144937214SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x20000 23244937214SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 23344937214SPrabhakar Kushwaha #define CONFIG_SPL_PAD_TO 0x20000 23444937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 23574cac00cSYuan Yao #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 2361f55a938SSantan Kumar #elif defined(CONFIG_SD_BOOT) 2370f4e1aceSSantan Kumar #define CONFIG_ENV_OFFSET 0x300000 2381f55a938SSantan Kumar #define CONFIG_SYS_MMC_ENV_DEV 0 2391f55a938SSantan Kumar #define CONFIG_ENV_SIZE 0x20000 240faed6bdeSSantan Kumar #endif 24144937214SPrabhakar Kushwaha #else 24244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 24344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 24444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 24544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 24644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 24744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 24844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 24944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 25044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 25144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 25244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 25344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 25444937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 25544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 25644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 25744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 25844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 25944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 26044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 26144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 26244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 26344937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 26444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 26544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 26644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 26744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 26844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 26944937214SPrabhakar Kushwaha 270*1908201cSRajesh Bhagat #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT) 271f5bf23d8SSantan Kumar #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 27244937214SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x20000 27344937214SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 27444937214SPrabhakar Kushwaha #endif 275a646f669SYuan Yao #endif 27644937214SPrabhakar Kushwaha 27744937214SPrabhakar Kushwaha /* Debug Server firmware */ 27844937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 27944937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 28044937214SPrabhakar Kushwaha 28144937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 28244937214SPrabhakar Kushwaha 28344937214SPrabhakar Kushwaha /* 28444937214SPrabhakar Kushwaha * I2C 28544937214SPrabhakar Kushwaha */ 28644937214SPrabhakar Kushwaha #define I2C_MUX_PCA_ADDR 0x77 28744937214SPrabhakar Kushwaha #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 28844937214SPrabhakar Kushwaha 28944937214SPrabhakar Kushwaha /* I2C bus multiplexer */ 29044937214SPrabhakar Kushwaha #define I2C_MUX_CH_DEFAULT 0x8 29144937214SPrabhakar Kushwaha 29244937214SPrabhakar Kushwaha /* SPI */ 293b718d371SYuan Yao #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 294b718d371SYuan Yao #ifdef CONFIG_FSL_DSPI 295b718d371SYuan Yao #define CONFIG_SPI_FLASH_STMICRO 296b718d371SYuan Yao #define CONFIG_SPI_FLASH_SST 297b718d371SYuan Yao #define CONFIG_SPI_FLASH_EON 298b718d371SYuan Yao #endif 299b718d371SYuan Yao 300b718d371SYuan Yao #ifdef CONFIG_FSL_QSPI 301b718d371SYuan Yao #define CONFIG_SPI_FLASH_SPANSION 302b718d371SYuan Yao #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 303b718d371SYuan Yao #define FSL_QSPI_FLASH_NUM 4 304b718d371SYuan Yao #endif 305453418f2SYuan Yao /* 306453418f2SYuan Yao * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 307453418f2SYuan Yao * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 308453418f2SYuan Yao * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 309453418f2SYuan Yao */ 310453418f2SYuan Yao #define FSL_QIXIS_BRDCFG9_QSPI 0x1 311b718d371SYuan Yao 31244937214SPrabhakar Kushwaha #endif 31344937214SPrabhakar Kushwaha 31444937214SPrabhakar Kushwaha /* 31544937214SPrabhakar Kushwaha * MMC 31644937214SPrabhakar Kushwaha */ 31744937214SPrabhakar Kushwaha #ifdef CONFIG_MMC 31844937214SPrabhakar Kushwaha #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 31944937214SPrabhakar Kushwaha QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 32044937214SPrabhakar Kushwaha #endif 32144937214SPrabhakar Kushwaha 32244937214SPrabhakar Kushwaha /* 32344937214SPrabhakar Kushwaha * RTC configuration 32444937214SPrabhakar Kushwaha */ 32544937214SPrabhakar Kushwaha #define RTC 32644937214SPrabhakar Kushwaha #define CONFIG_RTC_DS3231 1 32744937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_RTC_ADDR 0x68 32844937214SPrabhakar Kushwaha 32944937214SPrabhakar Kushwaha /* EEPROM */ 33044937214SPrabhakar Kushwaha #define CONFIG_ID_EEPROM 33144937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_NXID 33244937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_BUS_NUM 0 33344937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 33444937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 33544937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 33644937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 33744937214SPrabhakar Kushwaha 33844937214SPrabhakar Kushwaha #define CONFIG_FSL_MEMAC 33944937214SPrabhakar Kushwaha 34044937214SPrabhakar Kushwaha #ifdef CONFIG_PCI 34144937214SPrabhakar Kushwaha #define CONFIG_PCI_SCAN_SHOW 34244937214SPrabhakar Kushwaha #endif 34344937214SPrabhakar Kushwaha 34444937214SPrabhakar Kushwaha /* MMC */ 34544937214SPrabhakar Kushwaha #ifdef CONFIG_MMC 34644937214SPrabhakar Kushwaha #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 34744937214SPrabhakar Kushwaha #endif 34844937214SPrabhakar Kushwaha 34944937214SPrabhakar Kushwaha /* Initial environment variables */ 35044937214SPrabhakar Kushwaha #undef CONFIG_EXTRA_ENV_SETTINGS 3519ed44787SUdit Agarwal #ifdef CONFIG_SECURE_BOOT 3529ed44787SUdit Agarwal #define CONFIG_EXTRA_ENV_SETTINGS \ 3539ed44787SUdit Agarwal "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 3549ed44787SUdit Agarwal "loadaddr=0x80100000\0" \ 3559ed44787SUdit Agarwal "kernel_addr=0x100000\0" \ 3569ed44787SUdit Agarwal "ramdisk_addr=0x800000\0" \ 3579ed44787SUdit Agarwal "ramdisk_size=0x2000000\0" \ 3589ed44787SUdit Agarwal "fdt_high=0xa0000000\0" \ 3599ed44787SUdit Agarwal "initrd_high=0xffffffffffffffff\0" \ 3607676074aSUdit Agarwal "kernel_start=0x581000000\0" \ 3619ed44787SUdit Agarwal "kernel_load=0xa0000000\0" \ 3629ed44787SUdit Agarwal "kernel_size=0x2800000\0" \ 3636d7b9e78SSantan Kumar "mcmemsize=0x40000000\0" \ 3647676074aSUdit Agarwal "mcinitcmd=esbc_validate 0x580700000;" \ 3657676074aSUdit Agarwal "esbc_validate 0x580740000;" \ 3667676074aSUdit Agarwal "fsl_mc start mc 0x580a00000" \ 3677676074aSUdit Agarwal " 0x580e00000 \0" 368*1908201cSRajesh Bhagat #else 369*1908201cSRajesh Bhagat #ifdef CONFIG_TFABOOT 370*1908201cSRajesh Bhagat #define SD_MC_INIT_CMD \ 371*1908201cSRajesh Bhagat "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 372*1908201cSRajesh Bhagat "mmc read 0x80100000 0x7000 0x800;" \ 373*1908201cSRajesh Bhagat "fsl_mc start mc 0x80000000 0x80100000\0" 374*1908201cSRajesh Bhagat #define IFC_MC_INIT_CMD \ 375*1908201cSRajesh Bhagat "fsl_mc start mc 0x580a00000" \ 376*1908201cSRajesh Bhagat " 0x580e00000 \0" 377*1908201cSRajesh Bhagat #define CONFIG_EXTRA_ENV_SETTINGS \ 378*1908201cSRajesh Bhagat "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 379*1908201cSRajesh Bhagat "loadaddr=0x80100000\0" \ 380*1908201cSRajesh Bhagat "loadaddr_sd=0x90100000\0" \ 381*1908201cSRajesh Bhagat "kernel_addr=0x100000\0" \ 382*1908201cSRajesh Bhagat "kernel_addr_sd=0x800\0" \ 383*1908201cSRajesh Bhagat "ramdisk_addr=0x800000\0" \ 384*1908201cSRajesh Bhagat "ramdisk_size=0x2000000\0" \ 385*1908201cSRajesh Bhagat "fdt_high=0xa0000000\0" \ 386*1908201cSRajesh Bhagat "initrd_high=0xffffffffffffffff\0" \ 387*1908201cSRajesh Bhagat "kernel_start=0x581000000\0" \ 388*1908201cSRajesh Bhagat "kernel_start_sd=0x8000\0" \ 389*1908201cSRajesh Bhagat "kernel_load=0xa0000000\0" \ 390*1908201cSRajesh Bhagat "kernel_size=0x2800000\0" \ 391*1908201cSRajesh Bhagat "kernel_size_sd=0x14000\0" \ 392*1908201cSRajesh Bhagat "mcinitcmd=fsl_mc start mc 0x580a00000" \ 393*1908201cSRajesh Bhagat " 0x580e00000 \0" \ 394*1908201cSRajesh Bhagat "mcmemsize=0x70000000 \0" 3951f55a938SSantan Kumar #elif defined(CONFIG_SD_BOOT) 3961f55a938SSantan Kumar #define CONFIG_EXTRA_ENV_SETTINGS \ 3971f55a938SSantan Kumar "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 3981f55a938SSantan Kumar "loadaddr=0x90100000\0" \ 3991f55a938SSantan Kumar "kernel_addr=0x800\0" \ 4001f55a938SSantan Kumar "ramdisk_addr=0x800000\0" \ 4011f55a938SSantan Kumar "ramdisk_size=0x2000000\0" \ 4021f55a938SSantan Kumar "fdt_high=0xa0000000\0" \ 4031f55a938SSantan Kumar "initrd_high=0xffffffffffffffff\0" \ 4041f55a938SSantan Kumar "kernel_start=0x8000\0" \ 4051f55a938SSantan Kumar "kernel_load=0xa0000000\0" \ 4061f55a938SSantan Kumar "kernel_size=0x14000\0" \ 4071f55a938SSantan Kumar "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 4081f55a938SSantan Kumar "mmc read 0x80100000 0x7000 0x800;" \ 4091f55a938SSantan Kumar "fsl_mc start mc 0x80000000 0x80100000\0" \ 4101f55a938SSantan Kumar "mcmemsize=0x70000000 \0" 4119ed44787SUdit Agarwal #else 41244937214SPrabhakar Kushwaha #define CONFIG_EXTRA_ENV_SETTINGS \ 41344937214SPrabhakar Kushwaha "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 41444937214SPrabhakar Kushwaha "loadaddr=0x80100000\0" \ 41544937214SPrabhakar Kushwaha "kernel_addr=0x100000\0" \ 41644937214SPrabhakar Kushwaha "ramdisk_addr=0x800000\0" \ 41744937214SPrabhakar Kushwaha "ramdisk_size=0x2000000\0" \ 41844937214SPrabhakar Kushwaha "fdt_high=0xa0000000\0" \ 41944937214SPrabhakar Kushwaha "initrd_high=0xffffffffffffffff\0" \ 420f5bf23d8SSantan Kumar "kernel_start=0x581000000\0" \ 42144937214SPrabhakar Kushwaha "kernel_load=0xa0000000\0" \ 42216ed8560SPrabhakar Kushwaha "kernel_size=0x2800000\0" \ 4236d7b9e78SSantan Kumar "mcmemsize=0x40000000\0" \ 424f5bf23d8SSantan Kumar "mcinitcmd=fsl_mc start mc 0x580a00000" \ 425f5bf23d8SSantan Kumar " 0x580e00000 \0" 426*1908201cSRajesh Bhagat #endif /* CONFIG_TFABOOT */ 4279ed44787SUdit Agarwal #endif /* CONFIG_SECURE_BOOT */ 4289ed44787SUdit Agarwal 4291f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 43044937214SPrabhakar Kushwaha #define CONFIG_FSL_MEMAC 43144937214SPrabhakar Kushwaha #define CONFIG_PHYLIB_10G 43244937214SPrabhakar Kushwaha #define CONFIG_PHY_VITESSE 43344937214SPrabhakar Kushwaha #define CONFIG_PHY_REALTEK 43444937214SPrabhakar Kushwaha #define CONFIG_PHY_TERANETICS 43544937214SPrabhakar Kushwaha #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 43644937214SPrabhakar Kushwaha #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 43744937214SPrabhakar Kushwaha #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 43844937214SPrabhakar Kushwaha #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 43944937214SPrabhakar Kushwaha 44044937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 44144937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 44244937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 44344937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 44444937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 44544937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 44644937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 44744937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 44844937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 44944937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 45044937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 45144937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 45244937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 45344937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 45444937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 45544937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 45644937214SPrabhakar Kushwaha 4577ad9cc96SPrabhakar Kushwaha #define CONFIG_ETHPRIME "DPMAC1@xgmii" 45844937214SPrabhakar Kushwaha 45944937214SPrabhakar Kushwaha #endif 46044937214SPrabhakar Kushwaha 461fcfdb6d5SSaksham Jain #include <asm/fsl_secure_boot.h> 462fcfdb6d5SSaksham Jain 46344937214SPrabhakar Kushwaha #endif /* __LS2_QDS_H */ 464