144937214SPrabhakar Kushwaha /* 2*89a168f7SPriyanka Jain * Copyright 2017 NXP 344937214SPrabhakar Kushwaha * Copyright 2015 Freescale Semiconductor 444937214SPrabhakar Kushwaha * 544937214SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 644937214SPrabhakar Kushwaha */ 744937214SPrabhakar Kushwaha 844937214SPrabhakar Kushwaha #ifndef __LS2_QDS_H 944937214SPrabhakar Kushwaha #define __LS2_QDS_H 1044937214SPrabhakar Kushwaha 1144937214SPrabhakar Kushwaha #include "ls2080a_common.h" 1244937214SPrabhakar Kushwaha 1344937214SPrabhakar Kushwaha #ifndef __ASSEMBLY__ 1444937214SPrabhakar Kushwaha unsigned long get_board_sys_clk(void); 1544937214SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void); 1644937214SPrabhakar Kushwaha #endif 1744937214SPrabhakar Kushwaha 188c77ef85SYuan Yao #ifdef CONFIG_FSL_QSPI 198c77ef85SYuan Yao #undef CONFIG_CMD_IMLS 208c77ef85SYuan Yao #define CONFIG_QIXIS_I2C_ACCESS 218c77ef85SYuan Yao #define CONFIG_SYS_I2C_EARLY_INIT 228c77ef85SYuan Yao #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 238c77ef85SYuan Yao #endif 248c77ef85SYuan Yao 258c77ef85SYuan Yao #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 2644937214SPrabhakar Kushwaha #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 2744937214SPrabhakar Kushwaha #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 2844937214SPrabhakar Kushwaha #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 2944937214SPrabhakar Kushwaha 3044937214SPrabhakar Kushwaha #define CONFIG_DDR_SPD 3144937214SPrabhakar Kushwaha #define CONFIG_DDR_ECC 3244937214SPrabhakar Kushwaha #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 3344937214SPrabhakar Kushwaha #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 3444937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS1 0x51 3544937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS2 0x52 3644937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS3 0x53 3744937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS4 0x54 3844937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS5 0x55 3944937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 4044937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 4144937214SPrabhakar Kushwaha #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 4244937214SPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 2 4344937214SPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 4 4444937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 4544937214SPrabhakar Kushwaha #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 4644937214SPrabhakar Kushwaha #endif 4744937214SPrabhakar Kushwaha #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 4844937214SPrabhakar Kushwaha 49989c5f0aSTang Yuantian /* SATA */ 50989c5f0aSTang Yuantian #define CONFIG_LIBATA 51989c5f0aSTang Yuantian #define CONFIG_SCSI_AHCI 52989c5f0aSTang Yuantian #define CONFIG_SCSI_AHCI_PLAT 53c649e3c9SSimon Glass #define CONFIG_SCSI 54989c5f0aSTang Yuantian 55989c5f0aSTang Yuantian #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 56989c5f0aSTang Yuantian #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 57989c5f0aSTang Yuantian 58989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 59989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_LUN 1 60989c5f0aSTang Yuantian #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 61989c5f0aSTang Yuantian CONFIG_SYS_SCSI_MAX_LUN) 62989c5f0aSTang Yuantian 6344937214SPrabhakar Kushwaha /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 6444937214SPrabhakar Kushwaha 6544937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 6644937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 6744937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 6844937214SPrabhakar Kushwaha 6944937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR \ 7044937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 7144937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 7244937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 7344937214SPrabhakar Kushwaha CSPR_V) 7444937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EARLY \ 7544937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 7644937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 7744937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 7844937214SPrabhakar Kushwaha CSPR_V) 7944937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR1_CSPR \ 8044937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 8144937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 8244937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 8344937214SPrabhakar Kushwaha CSPR_V) 8444937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR1_CSPR_EARLY \ 8544937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 8644937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 8744937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 8844937214SPrabhakar Kushwaha CSPR_V) 8944937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 9044937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 9144937214SPrabhakar Kushwaha FTIM0_NOR_TEADC(0x5) | \ 9244937214SPrabhakar Kushwaha FTIM0_NOR_TEAHC(0x5)) 9344937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 9444937214SPrabhakar Kushwaha FTIM1_NOR_TRAD_NOR(0x1a) |\ 9544937214SPrabhakar Kushwaha FTIM1_NOR_TSEQRAD_NOR(0x13)) 9644937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 9744937214SPrabhakar Kushwaha FTIM2_NOR_TCH(0x4) | \ 9844937214SPrabhakar Kushwaha FTIM2_NOR_TWPH(0x0E) | \ 9944937214SPrabhakar Kushwaha FTIM2_NOR_TWP(0x1c)) 10044937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM3 0x04000000 10144937214SPrabhakar Kushwaha #define CONFIG_SYS_IFC_CCR 0x01000000 10244937214SPrabhakar Kushwaha 103e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH 10444937214SPrabhakar Kushwaha #define CONFIG_FLASH_CFI_DRIVER 10544937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_CFI 10644937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 10744937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_QUIET_TEST 10844937214SPrabhakar Kushwaha #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 10944937214SPrabhakar Kushwaha 11044937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 11144937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 11244937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 11344937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 11444937214SPrabhakar Kushwaha 11544937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_EMPTY_INFO 11644937214SPrabhakar Kushwaha #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 11744937214SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE + 0x40000000} 11844937214SPrabhakar Kushwaha #endif 11944937214SPrabhakar Kushwaha 12044937214SPrabhakar Kushwaha #define CONFIG_NAND_FSL_IFC 12144937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 256 12244937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 2 12344937214SPrabhakar Kushwaha 12444937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 12544937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 12644937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 12744937214SPrabhakar Kushwaha | CSPR_MSEL_NAND /* MSEL = NAND */ \ 12844937214SPrabhakar Kushwaha | CSPR_V) 12944937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 13044937214SPrabhakar Kushwaha 13144937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 13244937214SPrabhakar Kushwaha | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 13344937214SPrabhakar Kushwaha | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 13444937214SPrabhakar Kushwaha | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 13544937214SPrabhakar Kushwaha | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 13644937214SPrabhakar Kushwaha | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 13744937214SPrabhakar Kushwaha | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 13844937214SPrabhakar Kushwaha 13944937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_ONFI_DETECTION 14044937214SPrabhakar Kushwaha 14144937214SPrabhakar Kushwaha /* ONFI NAND Flash mode0 Timing Params */ 14244937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 14344937214SPrabhakar Kushwaha FTIM0_NAND_TWP(0x18) | \ 14444937214SPrabhakar Kushwaha FTIM0_NAND_TWCHT(0x07) | \ 14544937214SPrabhakar Kushwaha FTIM0_NAND_TWH(0x0a)) 14644937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 14744937214SPrabhakar Kushwaha FTIM1_NAND_TWBE(0x39) | \ 14844937214SPrabhakar Kushwaha FTIM1_NAND_TRR(0x0e) | \ 14944937214SPrabhakar Kushwaha FTIM1_NAND_TRP(0x18)) 15044937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 15144937214SPrabhakar Kushwaha FTIM2_NAND_TREH(0x0a) | \ 15244937214SPrabhakar Kushwaha FTIM2_NAND_TWHRE(0x1e)) 15344937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM3 0x0 15444937214SPrabhakar Kushwaha 15544937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 15644937214SPrabhakar Kushwaha #define CONFIG_SYS_MAX_NAND_DEVICE 1 15744937214SPrabhakar Kushwaha #define CONFIG_MTD_NAND_VERIFY_WRITE 15844937214SPrabhakar Kushwaha #define CONFIG_CMD_NAND 15944937214SPrabhakar Kushwaha 16044937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 16144937214SPrabhakar Kushwaha 16244937214SPrabhakar Kushwaha #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 16344937214SPrabhakar Kushwaha #define QIXIS_LBMAP_SWITCH 0x06 16444937214SPrabhakar Kushwaha #define QIXIS_LBMAP_MASK 0x0f 16544937214SPrabhakar Kushwaha #define QIXIS_LBMAP_SHIFT 0 16644937214SPrabhakar Kushwaha #define QIXIS_LBMAP_DFLTBANK 0x00 16744937214SPrabhakar Kushwaha #define QIXIS_LBMAP_ALTBANK 0x04 16844937214SPrabhakar Kushwaha #define QIXIS_LBMAP_NAND 0x09 169a646f669SYuan Yao #define QIXIS_LBMAP_QSPI 0x0f 17044937214SPrabhakar Kushwaha #define QIXIS_RST_CTL_RESET 0x31 17144937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 17244937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 17344937214SPrabhakar Kushwaha #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 17444937214SPrabhakar Kushwaha #define QIXIS_RCW_SRC_NAND 0x107 175a646f669SYuan Yao #define QIXIS_RCW_SRC_QSPI 0x62 17644937214SPrabhakar Kushwaha #define QIXIS_RST_FORCE_MEM 0x01 17744937214SPrabhakar Kushwaha 17844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3_EXT (0x0) 17944937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 18044937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 \ 18144937214SPrabhakar Kushwaha | CSPR_MSEL_GPCM \ 18244937214SPrabhakar Kushwaha | CSPR_V) 18344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 18444937214SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 \ 18544937214SPrabhakar Kushwaha | CSPR_MSEL_GPCM \ 18644937214SPrabhakar Kushwaha | CSPR_V) 18744937214SPrabhakar Kushwaha 18844937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 18944937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 19044937214SPrabhakar Kushwaha /* QIXIS Timing parameters for IFC CS3 */ 19144937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 19244937214SPrabhakar Kushwaha FTIM0_GPCM_TEADC(0x0e) | \ 19344937214SPrabhakar Kushwaha FTIM0_GPCM_TEAHC(0x0e)) 19444937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 19544937214SPrabhakar Kushwaha FTIM1_GPCM_TRAD(0x3f)) 19644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 19744937214SPrabhakar Kushwaha FTIM2_GPCM_TCH(0xf) | \ 19844937214SPrabhakar Kushwaha FTIM2_GPCM_TWP(0x3E)) 19944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS3_FTIM3 0x0 20044937214SPrabhakar Kushwaha 20144937214SPrabhakar Kushwaha #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 20244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 20344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 20444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 20544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 20644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 20744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 20844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 20944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 21044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 21144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 21244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 21344937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 21444937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 21544937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 21644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 21744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 21844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 21944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 22044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 22144937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 22244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 22344937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 22444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 22544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 22644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 22744937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 22844937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 22944937214SPrabhakar Kushwaha 23044937214SPrabhakar Kushwaha #define CONFIG_ENV_IS_IN_NAND 23144937214SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET (896 * 1024) 23244937214SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x20000 23344937214SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 23444937214SPrabhakar Kushwaha #define CONFIG_SPL_PAD_TO 0x20000 23544937214SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 23674cac00cSYuan Yao #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 23744937214SPrabhakar Kushwaha #else 23844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 23944937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 24044937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 24144937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 24244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 24344937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 24444937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 24544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 24644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 24744937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 24844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 24944937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 25044937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 25144937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 25244937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 25344937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 25444937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 25544937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 25644937214SPrabhakar Kushwaha #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 25744937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 25844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 25944937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 26044937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 26144937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 26244937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 26344937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 26444937214SPrabhakar Kushwaha #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 26544937214SPrabhakar Kushwaha 266*89a168f7SPriyanka Jain #ifndef CONFIG_QSPI_BOOT 26744937214SPrabhakar Kushwaha #define CONFIG_ENV_IS_IN_FLASH 26844937214SPrabhakar Kushwaha #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 26944937214SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x20000 27044937214SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 27144937214SPrabhakar Kushwaha #endif 272a646f669SYuan Yao #endif 27344937214SPrabhakar Kushwaha 27444937214SPrabhakar Kushwaha /* Debug Server firmware */ 27544937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 27644937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 27744937214SPrabhakar Kushwaha 27844937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 27944937214SPrabhakar Kushwaha 28044937214SPrabhakar Kushwaha /* 28144937214SPrabhakar Kushwaha * I2C 28244937214SPrabhakar Kushwaha */ 28344937214SPrabhakar Kushwaha #define I2C_MUX_PCA_ADDR 0x77 28444937214SPrabhakar Kushwaha #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 28544937214SPrabhakar Kushwaha 28644937214SPrabhakar Kushwaha /* I2C bus multiplexer */ 28744937214SPrabhakar Kushwaha #define I2C_MUX_CH_DEFAULT 0x8 28844937214SPrabhakar Kushwaha 28944937214SPrabhakar Kushwaha /* SPI */ 290b718d371SYuan Yao #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 29144937214SPrabhakar Kushwaha #define CONFIG_SPI_FLASH 292b718d371SYuan Yao 293b718d371SYuan Yao #ifdef CONFIG_FSL_DSPI 294b718d371SYuan Yao #define CONFIG_SPI_FLASH_STMICRO 295b718d371SYuan Yao #define CONFIG_SPI_FLASH_SST 296b718d371SYuan Yao #define CONFIG_SPI_FLASH_EON 297b718d371SYuan Yao #endif 298b718d371SYuan Yao 299b718d371SYuan Yao #ifdef CONFIG_FSL_QSPI 300b718d371SYuan Yao #define CONFIG_SPI_FLASH_SPANSION 301b718d371SYuan Yao #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 302b718d371SYuan Yao #define FSL_QSPI_FLASH_NUM 4 303b718d371SYuan Yao #endif 304453418f2SYuan Yao /* 305453418f2SYuan Yao * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 306453418f2SYuan Yao * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 307453418f2SYuan Yao * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 308453418f2SYuan Yao */ 309453418f2SYuan Yao #define FSL_QIXIS_BRDCFG9_QSPI 0x1 310b718d371SYuan Yao 31144937214SPrabhakar Kushwaha #endif 31244937214SPrabhakar Kushwaha 31344937214SPrabhakar Kushwaha /* 31444937214SPrabhakar Kushwaha * MMC 31544937214SPrabhakar Kushwaha */ 31644937214SPrabhakar Kushwaha #ifdef CONFIG_MMC 31744937214SPrabhakar Kushwaha #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 31844937214SPrabhakar Kushwaha QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 31944937214SPrabhakar Kushwaha #endif 32044937214SPrabhakar Kushwaha 32144937214SPrabhakar Kushwaha /* 32244937214SPrabhakar Kushwaha * RTC configuration 32344937214SPrabhakar Kushwaha */ 32444937214SPrabhakar Kushwaha #define RTC 32544937214SPrabhakar Kushwaha #define CONFIG_RTC_DS3231 1 32644937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_RTC_ADDR 0x68 32744937214SPrabhakar Kushwaha 32844937214SPrabhakar Kushwaha /* EEPROM */ 32944937214SPrabhakar Kushwaha #define CONFIG_ID_EEPROM 33044937214SPrabhakar Kushwaha #define CONFIG_CMD_EEPROM 33144937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_NXID 33244937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_BUS_NUM 0 33344937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 33444937214SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 33544937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 33644937214SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 33744937214SPrabhakar Kushwaha 33844937214SPrabhakar Kushwaha #define CONFIG_FSL_MEMAC 33944937214SPrabhakar Kushwaha 34044937214SPrabhakar Kushwaha #ifdef CONFIG_PCI 34144937214SPrabhakar Kushwaha #define CONFIG_PCI_SCAN_SHOW 34244937214SPrabhakar Kushwaha #define CONFIG_CMD_PCI 34344937214SPrabhakar Kushwaha #endif 34444937214SPrabhakar Kushwaha 34544937214SPrabhakar Kushwaha /* MMC */ 34644937214SPrabhakar Kushwaha #ifdef CONFIG_MMC 34744937214SPrabhakar Kushwaha #define CONFIG_FSL_ESDHC 34844937214SPrabhakar Kushwaha #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 34944937214SPrabhakar Kushwaha #endif 35044937214SPrabhakar Kushwaha 35144937214SPrabhakar Kushwaha /* Initial environment variables */ 35244937214SPrabhakar Kushwaha #undef CONFIG_EXTRA_ENV_SETTINGS 3539ed44787SUdit Agarwal #ifdef CONFIG_SECURE_BOOT 3549ed44787SUdit Agarwal #define CONFIG_EXTRA_ENV_SETTINGS \ 3559ed44787SUdit Agarwal "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 3569ed44787SUdit Agarwal "loadaddr=0x80100000\0" \ 3579ed44787SUdit Agarwal "kernel_addr=0x100000\0" \ 3589ed44787SUdit Agarwal "ramdisk_addr=0x800000\0" \ 3599ed44787SUdit Agarwal "ramdisk_size=0x2000000\0" \ 3609ed44787SUdit Agarwal "fdt_high=0xa0000000\0" \ 3619ed44787SUdit Agarwal "initrd_high=0xffffffffffffffff\0" \ 3629ed44787SUdit Agarwal "kernel_start=0x581100000\0" \ 3639ed44787SUdit Agarwal "kernel_load=0xa0000000\0" \ 3649ed44787SUdit Agarwal "kernel_size=0x2800000\0" \ 3656d7b9e78SSantan Kumar "mcmemsize=0x40000000\0" \ 3669ed44787SUdit Agarwal "mcinitcmd=esbc_validate 0x580c80000;" \ 3679ed44787SUdit Agarwal "esbc_validate 0x580cc0000;" \ 3689ed44787SUdit Agarwal "fsl_mc start mc 0x580300000" \ 3699ed44787SUdit Agarwal " 0x580800000 \0" 3709ed44787SUdit Agarwal #else 37144937214SPrabhakar Kushwaha #define CONFIG_EXTRA_ENV_SETTINGS \ 37244937214SPrabhakar Kushwaha "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 37344937214SPrabhakar Kushwaha "loadaddr=0x80100000\0" \ 37444937214SPrabhakar Kushwaha "kernel_addr=0x100000\0" \ 37544937214SPrabhakar Kushwaha "ramdisk_addr=0x800000\0" \ 37644937214SPrabhakar Kushwaha "ramdisk_size=0x2000000\0" \ 37744937214SPrabhakar Kushwaha "fdt_high=0xa0000000\0" \ 37844937214SPrabhakar Kushwaha "initrd_high=0xffffffffffffffff\0" \ 37944937214SPrabhakar Kushwaha "kernel_start=0x581100000\0" \ 38044937214SPrabhakar Kushwaha "kernel_load=0xa0000000\0" \ 38116ed8560SPrabhakar Kushwaha "kernel_size=0x2800000\0" \ 3826d7b9e78SSantan Kumar "mcmemsize=0x40000000\0" \ 38316ed8560SPrabhakar Kushwaha "mcinitcmd=fsl_mc start mc 0x580300000" \ 38416ed8560SPrabhakar Kushwaha " 0x580800000 \0" 3859ed44787SUdit Agarwal #endif /* CONFIG_SECURE_BOOT */ 3869ed44787SUdit Agarwal 38744937214SPrabhakar Kushwaha 38844937214SPrabhakar Kushwaha #ifdef CONFIG_FSL_MC_ENET 38944937214SPrabhakar Kushwaha #define CONFIG_FSL_MEMAC 39044937214SPrabhakar Kushwaha #define CONFIG_PHYLIB 39144937214SPrabhakar Kushwaha #define CONFIG_PHYLIB_10G 39244937214SPrabhakar Kushwaha #define CONFIG_PHY_VITESSE 39344937214SPrabhakar Kushwaha #define CONFIG_PHY_REALTEK 39444937214SPrabhakar Kushwaha #define CONFIG_PHY_TERANETICS 39544937214SPrabhakar Kushwaha #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 39644937214SPrabhakar Kushwaha #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 39744937214SPrabhakar Kushwaha #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 39844937214SPrabhakar Kushwaha #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 39944937214SPrabhakar Kushwaha 40044937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 40144937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 40244937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 40344937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 40444937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 40544937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 40644937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 40744937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 40844937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 40944937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 41044937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 41144937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 41244937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 41344937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 41444937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 41544937214SPrabhakar Kushwaha #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 41644937214SPrabhakar Kushwaha 41744937214SPrabhakar Kushwaha #define CONFIG_MII /* MII PHY management */ 4187ad9cc96SPrabhakar Kushwaha #define CONFIG_ETHPRIME "DPMAC1@xgmii" 41944937214SPrabhakar Kushwaha #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 42044937214SPrabhakar Kushwaha 42144937214SPrabhakar Kushwaha #endif 42244937214SPrabhakar Kushwaha 42344937214SPrabhakar Kushwaha /* 42444937214SPrabhakar Kushwaha * USB 42544937214SPrabhakar Kushwaha */ 42644937214SPrabhakar Kushwaha #define CONFIG_HAS_FSL_XHCI_USB 42744937214SPrabhakar Kushwaha #define CONFIG_USB_XHCI_FSL 42844937214SPrabhakar Kushwaha #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 42944937214SPrabhakar Kushwaha #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 43044937214SPrabhakar Kushwaha 431fcfdb6d5SSaksham Jain #include <asm/fsl_secure_boot.h> 432fcfdb6d5SSaksham Jain 43344937214SPrabhakar Kushwaha #endif /* __LS2_QDS_H */ 434