1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_SIMU_H 8 #define __LS2_SIMU_H 9 10 #include "ls2080a_common.h" 11 12 #define CONFIG_SYS_CLK_FREQ 100000000 13 #define CONFIG_DDR_CLK_FREQ 133333333 14 15 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 16 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 17 18 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 19 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 20 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 21 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 22 #endif 23 24 /* SMSC 91C111 ethernet configuration */ 25 #define CONFIG_SMC91111 26 #define CONFIG_SMC91111_BASE (0x2210000) 27 28 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 29 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 30 31 #ifdef CONFIG_MTD_NOR_FLASH 32 #define CONFIG_FLASH_CFI_DRIVER 33 #define CONFIG_SYS_FLASH_CFI 34 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 35 #define CONFIG_SYS_FLASH_QUIET_TEST 36 #endif 37 38 /* 39 * NOR Flash Timing Params 40 */ 41 #define CONFIG_SYS_NOR0_CSPR \ 42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 43 CSPR_PORT_SIZE_16 | \ 44 CSPR_MSEL_NOR | \ 45 CSPR_V) 46 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 48 CSPR_PORT_SIZE_16 | \ 49 CSPR_MSEL_NOR | \ 50 CSPR_V) 51 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 52 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 53 FTIM0_NOR_TEADC(0x1) | \ 54 FTIM0_NOR_TEAHC(0x1)) 55 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 56 FTIM1_NOR_TRAD_NOR(0x1)) 57 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 58 FTIM2_NOR_TCH(0x0) | \ 59 FTIM2_NOR_TWP(0x1)) 60 #define CONFIG_SYS_NOR_FTIM3 0x04000000 61 #define CONFIG_SYS_IFC_CCR 0x01000000 62 63 #ifdef CONFIG_MTD_NOR_FLASH 64 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 65 66 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 67 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 68 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 69 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 70 71 #define CONFIG_SYS_FLASH_EMPTY_INFO 72 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 73 #endif 74 75 #define CONFIG_NAND_FSL_IFC 76 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 77 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 78 79 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 80 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 81 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 82 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 83 | CSPR_V) 84 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 85 86 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 87 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 88 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 89 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 90 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 91 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 92 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 93 94 #define CONFIG_SYS_NAND_ONFI_DETECTION 95 96 /* ONFI NAND Flash mode0 Timing Params */ 97 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 98 FTIM0_NAND_TWP(0x18) | \ 99 FTIM0_NAND_TWCHT(0x07) | \ 100 FTIM0_NAND_TWH(0x0a)) 101 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 102 FTIM1_NAND_TWBE(0x39) | \ 103 FTIM1_NAND_TRR(0x0e) | \ 104 FTIM1_NAND_TRP(0x18)) 105 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 106 FTIM2_NAND_TREH(0x0a) | \ 107 FTIM2_NAND_TWHRE(0x1e)) 108 #define CONFIG_SYS_NAND_FTIM3 0x0 109 110 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 111 #define CONFIG_SYS_MAX_NAND_DEVICE 1 112 #define CONFIG_MTD_NAND_VERIFY_WRITE 113 #define CONFIG_CMD_NAND 114 115 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 116 117 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 118 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 119 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 120 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 121 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 122 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 123 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 124 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 125 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 126 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 127 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 128 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 129 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 130 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 131 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 132 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 133 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 134 135 /* MMC */ 136 #ifdef CONFIG_MMC 137 #define CONFIG_FSL_ESDHC 138 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 139 #endif 140 141 /* Debug Server firmware */ 142 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 143 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 144 145 /* MC firmware */ 146 #define CONFIG_SYS_LS_MC_DPL_IN_NOR 147 #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL 148 149 #define CONFIG_SYS_LS_MC_DPC_IN_NOR 150 #define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL 151 152 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 153 154 /* Store environment at top of flash */ 155 #define CONFIG_ENV_IS_NOWHERE 1 156 #define CONFIG_ENV_SIZE 0x1000 157 158 #endif /* __LS2_SIMU_H */ 159