1 /* 2 * Copyright 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_EMU_H 8 #define __LS2_EMU_H 9 10 #include "ls2080a_common.h" 11 12 #define CONFIG_SYS_CLK_FREQ 100000000 13 #define CONFIG_DDR_CLK_FREQ 133333333 14 15 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 16 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 17 18 #define CONFIG_DDR_SPD 19 #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ 20 #define SPD_EEPROM_ADDRESS1 0x51 21 #define SPD_EEPROM_ADDRESS2 0x52 22 #define SPD_EEPROM_ADDRESS3 0x53 23 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 24 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ 25 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 26 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 27 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 28 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 29 #endif 30 31 #define CONFIG_FSL_DDR_SYNC_REFRESH 32 33 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 34 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 35 /* 36 * NOR Flash Timing Params 37 */ 38 #define CONFIG_SYS_NOR0_CSPR \ 39 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 40 CSPR_PORT_SIZE_16 | \ 41 CSPR_MSEL_NOR | \ 42 CSPR_V) 43 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 44 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 45 CSPR_PORT_SIZE_16 | \ 46 CSPR_MSEL_NOR | \ 47 CSPR_V) 48 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 49 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 50 FTIM0_NOR_TEADC(0x1) | \ 51 FTIM0_NOR_TEAHC(0x1)) 52 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 53 FTIM1_NOR_TRAD_NOR(0x1)) 54 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 55 FTIM2_NOR_TCH(0x0) | \ 56 FTIM2_NOR_TWP(0x1)) 57 #define CONFIG_SYS_NOR_FTIM3 0x04000000 58 #define CONFIG_SYS_IFC_CCR 0x01000000 59 60 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 61 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 62 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 63 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 64 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 65 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 66 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 67 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 68 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 69 70 /* Debug Server firmware */ 71 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 72 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 73 74 /* 75 * This trick allows users to load MC images into DDR directly without 76 * copying from NOR flash. It dramatically improves speed. 77 */ 78 #define CONFIG_SYS_LS_MC_FW_IN_DDR 79 #define CONFIG_SYS_LS_MC_DPL_IN_DDR 80 #define CONFIG_SYS_LS_MC_DPC_IN_DDR 81 82 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 83 84 /* Store environment at top of flash */ 85 #define CONFIG_ENV_SIZE 0x1000 86 87 #endif /* __LS2_EMU_H */ 88