1 /* 2 * Copyright 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_EMU_H 8 #define __LS2_EMU_H 9 10 #include "ls2080a_common.h" 11 12 #ifdef CONFIG_LS2080A 13 #define CONFIG_IDENT_STRING " LS2080A-EMU" 14 #define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU" 15 #endif 16 17 #ifdef CONFIG_LS2085A 18 #define CONFIG_IDENT_STRING " LS2085A-EMU" 19 #define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU" 20 #endif 21 22 #define CONFIG_SYS_CLK_FREQ 100000000 23 #define CONFIG_DDR_CLK_FREQ 133333333 24 25 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 26 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 27 28 #define CONFIG_DDR_SPD 29 #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ 30 #define SPD_EEPROM_ADDRESS1 0x51 31 #define SPD_EEPROM_ADDRESS2 0x52 32 #define SPD_EEPROM_ADDRESS3 0x53 33 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 34 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ 35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 36 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 37 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 38 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 39 #endif 40 41 #define CONFIG_FSL_DDR_SYNC_REFRESH 42 43 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 44 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 45 /* 46 * NOR Flash Timing Params 47 */ 48 #define CONFIG_SYS_NOR0_CSPR \ 49 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 50 CSPR_PORT_SIZE_16 | \ 51 CSPR_MSEL_NOR | \ 52 CSPR_V) 53 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 54 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 55 CSPR_PORT_SIZE_16 | \ 56 CSPR_MSEL_NOR | \ 57 CSPR_V) 58 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 59 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 60 FTIM0_NOR_TEADC(0x1) | \ 61 FTIM0_NOR_TEAHC(0x1)) 62 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 63 FTIM1_NOR_TRAD_NOR(0x1)) 64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 65 FTIM2_NOR_TCH(0x0) | \ 66 FTIM2_NOR_TWP(0x1)) 67 #define CONFIG_SYS_NOR_FTIM3 0x04000000 68 #define CONFIG_SYS_IFC_CCR 0x01000000 69 70 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 71 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 72 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 73 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 74 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 75 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 76 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 77 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 78 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 79 80 /* Debug Server firmware */ 81 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 82 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 83 84 /* 85 * This trick allows users to load MC images into DDR directly without 86 * copying from NOR flash. It dramatically improves speed. 87 */ 88 #define CONFIG_SYS_LS_MC_FW_IN_DDR 89 #define CONFIG_SYS_LS_MC_DPL_IN_DDR 90 #define CONFIG_SYS_LS_MC_DPC_IN_DDR 91 92 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 93 94 /* Store environment at top of flash */ 95 #define CONFIG_ENV_IS_NOWHERE 1 96 #define CONFIG_ENV_SIZE 0x1000 97 98 #endif /* __LS2_EMU_H */ 99