1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_GICV3 13 #define CONFIG_FSL_TZPC_BP147 14 15 #include <asm/arch/stream_id_lsch3.h> 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #ifdef CONFIG_TFABOOT 20 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 21 #else 22 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 23 #endif 24 25 /* We need architecture specific misc initializations */ 26 27 /* Link Definitions */ 28 #ifndef CONFIG_TFABOOT 29 #ifndef CONFIG_QSPI_BOOT 30 #else 31 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 32 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 33 #define CONFIG_ENV_SECT_SIZE 0x40000 34 #endif 35 #endif 36 37 #define CONFIG_SKIP_LOWLEVEL_INIT 38 39 #ifndef CONFIG_SPL 40 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 41 #endif 42 #ifndef CONFIG_SYS_FSL_DDR4 43 #define CONFIG_SYS_DDR_RAW_TIMING 44 #endif 45 46 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 47 48 #define CONFIG_VERY_BIG_RAM 49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 50 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 52 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 53 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 54 55 /* 56 * SMP Definitinos 57 */ 58 #define CPU_RELEASE_ADDR secondary_boot_func 59 60 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 61 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 62 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 63 /* 64 * DDR controller use 0 as the base address for binding. 65 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 66 */ 67 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 68 #define CONFIG_DP_DDR_CTRL 2 69 #define CONFIG_DP_DDR_NUM_CTRLS 1 70 #endif 71 72 /* Generic Timer Definitions */ 73 /* 74 * This is not an accurate number. It is used in start.S. The frequency 75 * will be udpated later when get_bus_freq(0) is available. 76 */ 77 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 78 79 /* Size of malloc() pool */ 80 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 81 82 /* I2C */ 83 #define CONFIG_SYS_I2C 84 85 /* Serial Port */ 86 #define CONFIG_SYS_NS16550_SERIAL 87 #define CONFIG_SYS_NS16550_REG_SIZE 1 88 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 89 90 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 91 92 /* IFC */ 93 #define CONFIG_FSL_IFC 94 95 /* 96 * During booting, IFC is mapped at the region of 0x30000000. 97 * But this region is limited to 256MB. To accommodate NOR, promjet 98 * and FPGA. This region is divided as below: 99 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 100 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 101 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 102 * 103 * To accommodate bigger NOR flash and other devices, we will map IFC 104 * chip selects to as below: 105 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 106 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 107 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 108 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 109 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 110 * 111 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 112 * CONFIG_SYS_FLASH_BASE has the final address (core view) 113 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 114 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 115 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 116 */ 117 118 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 119 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 121 122 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 123 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 124 125 #ifndef __ASSEMBLY__ 126 unsigned long long get_qixis_addr(void); 127 #endif 128 #define QIXIS_BASE get_qixis_addr() 129 #define QIXIS_BASE_PHYS 0x20000000 130 #define QIXIS_BASE_PHYS_EARLY 0xC000000 131 #define QIXIS_STAT_PRES1 0xb 132 #define QIXIS_SDID_MASK 0x07 133 #define QIXIS_ESDHC_NO_ADAPTER 0x7 134 135 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 136 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 137 138 /* MC firmware */ 139 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 140 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 141 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 142 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 143 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 144 /* For LS2085A */ 145 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 146 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 147 148 /* Define phy_reset function to boot the MC based on mcinitcmd. 149 * This happens late enough to properly fixup u-boot env MAC addresses. 150 */ 151 #define CONFIG_RESET_PHY_R 152 153 /* 154 * Carve out a DDR region which will not be used by u-boot/Linux 155 * 156 * It will be used by MC and Debug Server. The MC region must be 157 * 512MB aligned, so the min size to hide is 512MB. 158 */ 159 #ifdef CONFIG_FSL_MC_ENET 160 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 161 #endif 162 163 /* Command line configuration */ 164 165 /* Miscellaneous configurable options */ 166 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 167 168 /* Physical Memory Map */ 169 /* fixme: these need to be checked against the board */ 170 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 171 172 #define CONFIG_HWCONFIG 173 #define HWCONFIG_BUFFER_SIZE 128 174 175 /* Allow to overwrite serial and ethaddr */ 176 #define CONFIG_ENV_OVERWRITE 177 178 /* Initial environment variables */ 179 #define CONFIG_EXTRA_ENV_SETTINGS \ 180 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 181 "loadaddr=0x80100000\0" \ 182 "kernel_addr=0x100000\0" \ 183 "ramdisk_addr=0x800000\0" \ 184 "ramdisk_size=0x2000000\0" \ 185 "fdt_high=0xa0000000\0" \ 186 "initrd_high=0xffffffffffffffff\0" \ 187 "kernel_start=0x581000000\0" \ 188 "kernel_load=0xa0000000\0" \ 189 "kernel_size=0x2800000\0" \ 190 "console=ttyAMA0,38400n8\0" \ 191 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 192 " 0x580e00000 \0" 193 194 #ifndef CONFIG_TFABOOT 195 #ifdef CONFIG_SD_BOOT 196 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 197 " fsl_mc apply dpl 0x80200000 &&" \ 198 " mmc read $kernel_load $kernel_start" \ 199 " $kernel_size && bootm $kernel_load" 200 #else 201 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 202 " cp.b $kernel_start $kernel_load" \ 203 " $kernel_size && bootm $kernel_load" 204 #endif 205 #endif 206 207 /* Monitor Command Prompt */ 208 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 209 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 210 211 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 212 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 213 #define CONFIG_SPL_MAX_SIZE 0x16000 214 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 215 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 216 #define CONFIG_SPL_TEXT_BASE 0x1800a000 217 218 #ifdef CONFIG_NAND_BOOT 219 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 220 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 221 #endif 222 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 223 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 224 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 225 226 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 227 228 #include <asm/arch/soc.h> 229 230 #endif /* __LS2_COMMON_H */ 231