1 /*
2  * Copyright (C) 2014 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS2_COMMON_H
8 #define __LS2_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_MP
13 #define CONFIG_GICV3
14 #define CONFIG_FSL_TZPC_BP147
15 
16 #include <asm/arch/ls2080a_stream_id.h>
17 #include <asm/arch/config.h>
18 
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
21 
22 /* We need architecture specific misc initializations */
23 
24 /* Link Definitions */
25 #ifndef CONFIG_QSPI_BOOT
26 #ifdef CONFIG_SPL
27 #define CONFIG_SYS_TEXT_BASE		0x80400000
28 #else
29 #define CONFIG_SYS_TEXT_BASE		0x30100000
30 #endif
31 #endif
32 
33 #define CONFIG_SUPPORT_RAW_INITRD
34 
35 #define CONFIG_SKIP_LOWLEVEL_INIT
36 
37 #ifndef CONFIG_SPL
38 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
39 #endif
40 #ifndef CONFIG_SYS_FSL_DDR4
41 #define CONFIG_SYS_DDR_RAW_TIMING
42 #endif
43 
44 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
45 
46 #define CONFIG_VERY_BIG_RAM
47 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
48 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
49 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
50 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
51 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
52 
53 /*
54  * SMP Definitinos
55  */
56 #define CPU_RELEASE_ADDR		secondary_boot_func
57 
58 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
59 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60 #define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
61 /*
62  * DDR controller use 0 as the base address for binding.
63  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
64  */
65 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
66 #define CONFIG_DP_DDR_CTRL		2
67 #define CONFIG_DP_DDR_NUM_CTRLS		1
68 #endif
69 
70 /* Generic Timer Definitions */
71 /*
72  * This is not an accurate number. It is used in start.S. The frequency
73  * will be udpated later when get_bus_freq(0) is available.
74  */
75 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
76 
77 /* Size of malloc() pool */
78 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
79 
80 /* I2C */
81 #define CONFIG_SYS_I2C
82 #define CONFIG_SYS_I2C_MXC
83 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
84 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
85 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
86 #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
87 
88 /* Serial Port */
89 #define CONFIG_CONS_INDEX       1
90 #define CONFIG_SYS_NS16550_SERIAL
91 #define CONFIG_SYS_NS16550_REG_SIZE     1
92 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
93 
94 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
95 
96 /* IFC */
97 #define CONFIG_FSL_IFC
98 
99 /*
100  * During booting, IFC is mapped at the region of 0x30000000.
101  * But this region is limited to 256MB. To accommodate NOR, promjet
102  * and FPGA. This region is divided as below:
103  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
104  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
105  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
106  *
107  * To accommodate bigger NOR flash and other devices, we will map IFC
108  * chip selects to as below:
109  * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
110  * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
111  * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
112  * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
113  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
114  *
115  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
116  * CONFIG_SYS_FLASH_BASE has the final address (core view)
117  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
118  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
119  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
120  */
121 
122 #define CONFIG_SYS_FLASH_BASE			0x580000000ULL
123 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
124 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
125 
126 #define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
127 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
128 
129 #ifndef __ASSEMBLY__
130 unsigned long long get_qixis_addr(void);
131 #endif
132 #define QIXIS_BASE				get_qixis_addr()
133 #define QIXIS_BASE_PHYS				0x20000000
134 #define QIXIS_BASE_PHYS_EARLY			0xC000000
135 #define QIXIS_STAT_PRES1			0xb
136 #define QIXIS_SDID_MASK				0x07
137 #define QIXIS_ESDHC_NO_ADAPTER			0x7
138 
139 #define CONFIG_SYS_NAND_BASE			0x530000000ULL
140 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
141 
142 /* MC firmware */
143 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
144 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
145 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
146 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
147 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
148 /* For LS2085A */
149 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
150 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
151 
152 /*
153  * Carve out a DDR region which will not be used by u-boot/Linux
154  *
155  * It will be used by MC and Debug Server. The MC region must be
156  * 512MB aligned, so the min size to hide is 512MB.
157  */
158 #ifdef CONFIG_FSL_MC_ENET
159 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
160 #endif
161 
162 /* Command line configuration */
163 #define CONFIG_CMD_ENV
164 
165 /* Miscellaneous configurable options */
166 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
167 
168 /* Physical Memory Map */
169 /* fixme: these need to be checked against the board */
170 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
171 
172 #define CONFIG_NR_DRAM_BANKS		3
173 
174 #define CONFIG_HWCONFIG
175 #define HWCONFIG_BUFFER_SIZE		128
176 
177 /* Allow to overwrite serial and ethaddr */
178 #define CONFIG_ENV_OVERWRITE
179 
180 /* Initial environment variables */
181 #define CONFIG_EXTRA_ENV_SETTINGS		\
182 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
183 	"loadaddr=0x80100000\0"			\
184 	"kernel_addr=0x100000\0"		\
185 	"ramdisk_addr=0x800000\0"		\
186 	"ramdisk_size=0x2000000\0"		\
187 	"fdt_high=0xa0000000\0"			\
188 	"initrd_high=0xffffffffffffffff\0"	\
189 	"kernel_start=0x581200000\0"		\
190 	"kernel_load=0xa0000000\0"		\
191 	"kernel_size=0x2800000\0"		\
192 	"console=ttyAMA0,38400n8\0"		\
193 	"mcinitcmd=fsl_mc start mc 0x580300000"	\
194 	" 0x580800000 \0"
195 
196 #define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
197 				"earlycon=uart8250,mmio,0x21c0500 " \
198 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
199 				" hugepagesz=2m hugepages=256"
200 #define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
201 				" cp.b $kernel_start $kernel_load" \
202 				" $kernel_size && bootm $kernel_load"
203 
204 /* Monitor Command Prompt */
205 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
206 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
207 					sizeof(CONFIG_SYS_PROMPT) + 16)
208 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
209 #define CONFIG_SYS_LONGHELP
210 #define CONFIG_CMDLINE_EDITING		1
211 #define CONFIG_AUTO_COMPLETE
212 #define CONFIG_SYS_MAXARGS		64	/* max command args */
213 
214 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
215 
216 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
217 #define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
218 #define CONFIG_SPL_FRAMEWORK
219 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
220 #define CONFIG_SPL_MAX_SIZE		0x16000
221 #define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
222 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
223 #define CONFIG_SPL_TEXT_BASE		0x1800a000
224 
225 #define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
226 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
227 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
228 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
229 #define CONFIG_SYS_MONITOR_LEN		(640 * 1024)
230 
231 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
232 
233 /* Hash command with SHA acceleration supported in hardware */
234 #ifdef CONFIG_FSL_CAAM
235 #define CONFIG_CMD_HASH
236 #define CONFIG_SHA_HW_ACCEL
237 #endif
238 
239 #endif /* __LS2_COMMON_H */
240