1 /* 2 * Copyright 2017 NXP 3 * Copyright (C) 2014 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_COMMON_H 9 #define __LS2_COMMON_H 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_MP 14 #define CONFIG_GICV3 15 #define CONFIG_FSL_TZPC_BP147 16 17 #include <asm/arch/stream_id_lsch3.h> 18 #include <asm/arch/config.h> 19 20 /* Link Definitions */ 21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 22 23 /* We need architecture specific misc initializations */ 24 25 /* Link Definitions */ 26 #ifndef CONFIG_QSPI_BOOT 27 #else 28 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 29 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 30 #define CONFIG_ENV_SECT_SIZE 0x40000 31 #endif 32 33 #define CONFIG_SKIP_LOWLEVEL_INIT 34 35 #ifndef CONFIG_SPL 36 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 37 #endif 38 #ifndef CONFIG_SYS_FSL_DDR4 39 #define CONFIG_SYS_DDR_RAW_TIMING 40 #endif 41 42 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 49 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 50 51 /* 52 * SMP Definitinos 53 */ 54 #define CPU_RELEASE_ADDR secondary_boot_func 55 56 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 58 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 59 /* 60 * DDR controller use 0 as the base address for binding. 61 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 62 */ 63 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 64 #define CONFIG_DP_DDR_CTRL 2 65 #define CONFIG_DP_DDR_NUM_CTRLS 1 66 #endif 67 68 /* Generic Timer Definitions */ 69 /* 70 * This is not an accurate number. It is used in start.S. The frequency 71 * will be udpated later when get_bus_freq(0) is available. 72 */ 73 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 74 75 /* Size of malloc() pool */ 76 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 81 /* Serial Port */ 82 #define CONFIG_SYS_NS16550_SERIAL 83 #define CONFIG_SYS_NS16550_REG_SIZE 1 84 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 85 86 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 87 88 /* IFC */ 89 #define CONFIG_FSL_IFC 90 91 /* 92 * During booting, IFC is mapped at the region of 0x30000000. 93 * But this region is limited to 256MB. To accommodate NOR, promjet 94 * and FPGA. This region is divided as below: 95 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 96 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 97 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 98 * 99 * To accommodate bigger NOR flash and other devices, we will map IFC 100 * chip selects to as below: 101 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 102 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 103 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 104 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 105 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 106 * 107 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 108 * CONFIG_SYS_FLASH_BASE has the final address (core view) 109 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 110 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 111 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 112 */ 113 114 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 115 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 116 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 117 118 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 119 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 120 121 #ifndef __ASSEMBLY__ 122 unsigned long long get_qixis_addr(void); 123 #endif 124 #define QIXIS_BASE get_qixis_addr() 125 #define QIXIS_BASE_PHYS 0x20000000 126 #define QIXIS_BASE_PHYS_EARLY 0xC000000 127 #define QIXIS_STAT_PRES1 0xb 128 #define QIXIS_SDID_MASK 0x07 129 #define QIXIS_ESDHC_NO_ADAPTER 0x7 130 131 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 132 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 133 134 /* MC firmware */ 135 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 136 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 137 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 138 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 139 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 140 /* For LS2085A */ 141 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 142 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 143 144 /* Define phy_reset function to boot the MC based on mcinitcmd. 145 * This happens late enough to properly fixup u-boot env MAC addresses. 146 */ 147 #define CONFIG_RESET_PHY_R 148 149 /* 150 * Carve out a DDR region which will not be used by u-boot/Linux 151 * 152 * It will be used by MC and Debug Server. The MC region must be 153 * 512MB aligned, so the min size to hide is 512MB. 154 */ 155 #ifdef CONFIG_FSL_MC_ENET 156 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 157 #endif 158 159 /* Command line configuration */ 160 161 /* Miscellaneous configurable options */ 162 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 163 164 /* Physical Memory Map */ 165 /* fixme: these need to be checked against the board */ 166 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 167 168 #define CONFIG_NR_DRAM_BANKS 3 169 170 #define CONFIG_HWCONFIG 171 #define HWCONFIG_BUFFER_SIZE 128 172 173 /* Allow to overwrite serial and ethaddr */ 174 #define CONFIG_ENV_OVERWRITE 175 176 /* Initial environment variables */ 177 #define CONFIG_EXTRA_ENV_SETTINGS \ 178 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 179 "loadaddr=0x80100000\0" \ 180 "kernel_addr=0x100000\0" \ 181 "ramdisk_addr=0x800000\0" \ 182 "ramdisk_size=0x2000000\0" \ 183 "fdt_high=0xa0000000\0" \ 184 "initrd_high=0xffffffffffffffff\0" \ 185 "kernel_start=0x581000000\0" \ 186 "kernel_load=0xa0000000\0" \ 187 "kernel_size=0x2800000\0" \ 188 "console=ttyAMA0,38400n8\0" \ 189 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 190 " 0x580e00000 \0" 191 192 #ifdef CONFIG_SD_BOOT 193 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 194 " fsl_mc apply dpl 0x80200000 &&" \ 195 " mmc read $kernel_load $kernel_start" \ 196 " $kernel_size && bootm $kernel_load" 197 #else 198 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 199 " cp.b $kernel_start $kernel_load" \ 200 " $kernel_size && bootm $kernel_load" 201 #endif 202 203 /* Monitor Command Prompt */ 204 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 205 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 206 207 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 208 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 209 #define CONFIG_SPL_MAX_SIZE 0x16000 210 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 211 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 212 #define CONFIG_SPL_TEXT_BASE 0x1800a000 213 214 #ifdef CONFIG_NAND_BOOT 215 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 216 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 217 #endif 218 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 219 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 220 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 221 222 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 223 224 #include <asm/arch/soc.h> 225 226 #endif /* __LS2_COMMON_H */ 227