1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_FSL_LSCH3 14 #define CONFIG_MP 15 #define CONFIG_GICV3 16 #define CONFIG_FSL_TZPC_BP147 17 18 19 #include <asm/arch/ls2080a_stream_id.h> 20 #include <asm/arch/config.h> 21 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) 22 #define CONFIG_SYS_HAS_SERDES 23 #endif 24 25 /* Link Definitions */ 26 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 27 28 /* We need architecture specific misc initializations */ 29 #define CONFIG_ARCH_MISC_INIT 30 31 /* Link Definitions */ 32 #ifdef CONFIG_SPL 33 #define CONFIG_SYS_TEXT_BASE 0x80400000 34 #else 35 #define CONFIG_SYS_TEXT_BASE 0x30100000 36 #endif 37 38 #ifdef CONFIG_EMU 39 #define CONFIG_SYS_NO_FLASH 40 #endif 41 42 #define CONFIG_SUPPORT_RAW_INITRD 43 44 #define CONFIG_SKIP_LOWLEVEL_INIT 45 #define CONFIG_BOARD_EARLY_INIT_F 1 46 47 /* Flat Device Tree Definitions */ 48 #define CONFIG_OF_LIBFDT 49 #define CONFIG_OF_BOARD_SETUP 50 #define CONFIG_OF_STDOUT_VIA_ALIAS 51 52 /* new uImage format support */ 53 #define CONFIG_FIT 54 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 55 56 #ifndef CONFIG_SPL 57 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 58 #endif 59 #ifndef CONFIG_SYS_FSL_DDR4 60 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 61 #define CONFIG_SYS_DDR_RAW_TIMING 62 #endif 63 64 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 65 66 #define CONFIG_VERY_BIG_RAM 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 68 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 70 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 71 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 72 73 /* 74 * SMP Definitinos 75 */ 76 #define CPU_RELEASE_ADDR secondary_boot_func 77 78 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 79 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 80 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 81 /* 82 * DDR controller use 0 as the base address for binding. 83 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 84 */ 85 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 86 #define CONFIG_DP_DDR_CTRL 2 87 #define CONFIG_DP_DDR_NUM_CTRLS 1 88 #endif 89 90 /* Generic Timer Definitions */ 91 /* 92 * This is not an accurate number. It is used in start.S. The frequency 93 * will be udpated later when get_bus_freq(0) is available. 94 */ 95 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 96 97 /* Size of malloc() pool */ 98 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 99 100 /* I2C */ 101 #define CONFIG_CMD_I2C 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_I2C_MXC 104 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 105 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 106 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 107 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 108 109 /* Serial Port */ 110 #define CONFIG_CONS_INDEX 1 111 #define CONFIG_SYS_NS16550_SERIAL 112 #define CONFIG_SYS_NS16550_REG_SIZE 1 113 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 114 115 #define CONFIG_BAUDRATE 115200 116 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 117 118 /* IFC */ 119 #define CONFIG_FSL_IFC 120 121 /* 122 * During booting, IFC is mapped at the region of 0x30000000. 123 * But this region is limited to 256MB. To accommodate NOR, promjet 124 * and FPGA. This region is divided as below: 125 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 126 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 127 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 128 * 129 * To accommodate bigger NOR flash and other devices, we will map IFC 130 * chip selects to as below: 131 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 132 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 133 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 134 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 135 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 136 * 137 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 138 * CONFIG_SYS_FLASH_BASE has the final address (core view) 139 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 140 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 141 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 142 */ 143 144 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 145 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 146 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 147 148 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 149 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 150 151 #ifndef CONFIG_SYS_NO_FLASH 152 #define CONFIG_FLASH_CFI_DRIVER 153 #define CONFIG_SYS_FLASH_CFI 154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 155 #define CONFIG_SYS_FLASH_QUIET_TEST 156 #endif 157 158 #ifndef __ASSEMBLY__ 159 unsigned long long get_qixis_addr(void); 160 #endif 161 #define QIXIS_BASE get_qixis_addr() 162 #define QIXIS_BASE_PHYS 0x20000000 163 #define QIXIS_BASE_PHYS_EARLY 0xC000000 164 #define QIXIS_STAT_PRES1 0xb 165 #define QIXIS_SDID_MASK 0x07 166 #define QIXIS_ESDHC_NO_ADAPTER 0x7 167 168 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 169 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 170 171 /* Debug Server firmware */ 172 #define CONFIG_FSL_DEBUG_SERVER 173 /* 2 sec timeout */ 174 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) 175 176 /* MC firmware */ 177 #define CONFIG_FSL_MC_ENET 178 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 179 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 180 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 181 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 182 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 183 #ifdef CONFIG_LS2085A 184 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 185 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 186 #endif 187 188 /* 189 * Carve out a DDR region which will not be used by u-boot/Linux 190 * 191 * It will be used by MC and Debug Server. The MC region must be 192 * 512MB aligned, so the min size to hide is 512MB. 193 */ 194 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) 195 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) 196 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 197 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 198 #endif 199 200 /* PCIe */ 201 #define CONFIG_PCIE1 /* PCIE controler 1 */ 202 #define CONFIG_PCIE2 /* PCIE controler 2 */ 203 #define CONFIG_PCIE3 /* PCIE controler 3 */ 204 #define CONFIG_PCIE4 /* PCIE controler 4 */ 205 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 206 #ifdef CONFIG_LS2080A 207 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" 208 #endif 209 210 #ifdef CONFIG_LS2085A 211 #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" 212 #endif 213 214 #define CONFIG_SYS_PCI_64BIT 215 216 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 217 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 218 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 219 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 220 221 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 222 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 223 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 224 225 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 226 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 227 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 228 229 /* Command line configuration */ 230 #define CONFIG_CMD_CACHE 231 #define CONFIG_CMD_DHCP 232 #define CONFIG_CMD_ENV 233 #define CONFIG_CMD_GREPENV 234 #define CONFIG_CMD_MII 235 #define CONFIG_CMD_PING 236 237 /* Miscellaneous configurable options */ 238 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 239 #define CONFIG_ARCH_EARLY_INIT_R 240 241 /* Physical Memory Map */ 242 /* fixme: these need to be checked against the board */ 243 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 244 245 #define CONFIG_NR_DRAM_BANKS 3 246 247 #define CONFIG_HWCONFIG 248 #define HWCONFIG_BUFFER_SIZE 128 249 250 #define CONFIG_DISPLAY_CPUINFO 251 252 /* Allow to overwrite serial and ethaddr */ 253 #define CONFIG_ENV_OVERWRITE 254 255 /* Initial environment variables */ 256 #define CONFIG_EXTRA_ENV_SETTINGS \ 257 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 258 "loadaddr=0x80100000\0" \ 259 "kernel_addr=0x100000\0" \ 260 "ramdisk_addr=0x800000\0" \ 261 "ramdisk_size=0x2000000\0" \ 262 "fdt_high=0xa0000000\0" \ 263 "initrd_high=0xffffffffffffffff\0" \ 264 "kernel_start=0x581200000\0" \ 265 "kernel_load=0xa0000000\0" \ 266 "kernel_size=0x2800000\0" \ 267 "console=ttyAMA0,38400n8\0" 268 269 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 270 "earlycon=uart8250,mmio,0x21c0500" \ 271 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 272 " hugepagesz=2m hugepages=16" 273 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 274 "$kernel_size && bootm $kernel_load" 275 #define CONFIG_BOOTDELAY 10 276 277 /* Monitor Command Prompt */ 278 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 279 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 280 sizeof(CONFIG_SYS_PROMPT) + 16) 281 #define CONFIG_SYS_HUSH_PARSER 282 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 283 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 284 #define CONFIG_SYS_LONGHELP 285 #define CONFIG_CMDLINE_EDITING 1 286 #define CONFIG_AUTO_COMPLETE 287 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 288 289 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 290 291 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 292 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 293 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 294 #define CONFIG_SPL_ENV_SUPPORT 295 #define CONFIG_SPL_FRAMEWORK 296 #define CONFIG_SPL_I2C_SUPPORT 297 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 298 #define CONFIG_SPL_LIBCOMMON_SUPPORT 299 #define CONFIG_SPL_LIBGENERIC_SUPPORT 300 #define CONFIG_SPL_MAX_SIZE 0x16000 301 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 302 #define CONFIG_SPL_NAND_SUPPORT 303 #define CONFIG_SPL_SERIAL_SUPPORT 304 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 305 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 306 #define CONFIG_SPL_TEXT_BASE 0x1800a000 307 308 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 309 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 310 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 311 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 312 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 313 314 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 315 316 317 #endif /* __LS2_COMMON_H */ 318