1 /* 2 * Copyright 2017 NXP 3 * Copyright (C) 2014 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_COMMON_H 9 #define __LS2_COMMON_H 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_MP 14 #define CONFIG_GICV3 15 #define CONFIG_FSL_TZPC_BP147 16 17 #include <asm/arch/stream_id_lsch3.h> 18 #include <asm/arch/config.h> 19 20 /* Link Definitions */ 21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 22 23 /* We need architecture specific misc initializations */ 24 25 /* Link Definitions */ 26 #ifndef CONFIG_QSPI_BOOT 27 #else 28 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 29 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 30 #define CONFIG_ENV_SECT_SIZE 0x40000 31 #endif 32 33 #define CONFIG_SKIP_LOWLEVEL_INIT 34 35 #ifndef CONFIG_SPL 36 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 37 #endif 38 #ifndef CONFIG_SYS_FSL_DDR4 39 #define CONFIG_SYS_DDR_RAW_TIMING 40 #endif 41 42 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 49 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 50 51 /* 52 * SMP Definitinos 53 */ 54 #define CPU_RELEASE_ADDR secondary_boot_func 55 56 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 58 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 59 /* 60 * DDR controller use 0 as the base address for binding. 61 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 62 */ 63 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 64 #define CONFIG_DP_DDR_CTRL 2 65 #define CONFIG_DP_DDR_NUM_CTRLS 1 66 #endif 67 68 /* Generic Timer Definitions */ 69 /* 70 * This is not an accurate number. It is used in start.S. The frequency 71 * will be udpated later when get_bus_freq(0) is available. 72 */ 73 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 74 75 /* Size of malloc() pool */ 76 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C_MXC 81 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 82 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 83 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 84 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 85 86 /* Serial Port */ 87 #define CONFIG_SYS_NS16550_SERIAL 88 #define CONFIG_SYS_NS16550_REG_SIZE 1 89 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 90 91 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 92 93 /* IFC */ 94 #define CONFIG_FSL_IFC 95 96 /* 97 * During booting, IFC is mapped at the region of 0x30000000. 98 * But this region is limited to 256MB. To accommodate NOR, promjet 99 * and FPGA. This region is divided as below: 100 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 101 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 102 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 103 * 104 * To accommodate bigger NOR flash and other devices, we will map IFC 105 * chip selects to as below: 106 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 107 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 108 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 109 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 110 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 111 * 112 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 113 * CONFIG_SYS_FLASH_BASE has the final address (core view) 114 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 115 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 116 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 117 */ 118 119 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 120 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 121 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 122 123 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 124 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 125 126 #ifndef __ASSEMBLY__ 127 unsigned long long get_qixis_addr(void); 128 #endif 129 #define QIXIS_BASE get_qixis_addr() 130 #define QIXIS_BASE_PHYS 0x20000000 131 #define QIXIS_BASE_PHYS_EARLY 0xC000000 132 #define QIXIS_STAT_PRES1 0xb 133 #define QIXIS_SDID_MASK 0x07 134 #define QIXIS_ESDHC_NO_ADAPTER 0x7 135 136 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 137 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 138 139 /* MC firmware */ 140 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 141 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 142 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 143 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 144 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 145 /* For LS2085A */ 146 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 147 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 148 149 /* Define phy_reset function to boot the MC based on mcinitcmd. 150 * This happens late enough to properly fixup u-boot env MAC addresses. 151 */ 152 #define CONFIG_RESET_PHY_R 153 154 /* 155 * Carve out a DDR region which will not be used by u-boot/Linux 156 * 157 * It will be used by MC and Debug Server. The MC region must be 158 * 512MB aligned, so the min size to hide is 512MB. 159 */ 160 #ifdef CONFIG_FSL_MC_ENET 161 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 162 #endif 163 164 /* Command line configuration */ 165 166 /* Miscellaneous configurable options */ 167 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 168 169 /* Physical Memory Map */ 170 /* fixme: these need to be checked against the board */ 171 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 172 173 #define CONFIG_NR_DRAM_BANKS 3 174 175 #define CONFIG_HWCONFIG 176 #define HWCONFIG_BUFFER_SIZE 128 177 178 /* Allow to overwrite serial and ethaddr */ 179 #define CONFIG_ENV_OVERWRITE 180 181 /* Initial environment variables */ 182 #define CONFIG_EXTRA_ENV_SETTINGS \ 183 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 184 "loadaddr=0x80100000\0" \ 185 "kernel_addr=0x100000\0" \ 186 "ramdisk_addr=0x800000\0" \ 187 "ramdisk_size=0x2000000\0" \ 188 "fdt_high=0xa0000000\0" \ 189 "initrd_high=0xffffffffffffffff\0" \ 190 "kernel_start=0x581000000\0" \ 191 "kernel_load=0xa0000000\0" \ 192 "kernel_size=0x2800000\0" \ 193 "console=ttyAMA0,38400n8\0" \ 194 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 195 " 0x580e00000 \0" 196 197 #ifdef CONFIG_SD_BOOT 198 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 199 " fsl_mc apply dpl 0x80200000 &&" \ 200 " mmc read $kernel_load $kernel_start" \ 201 " $kernel_size && bootm $kernel_load" 202 #else 203 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 204 " cp.b $kernel_start $kernel_load" \ 205 " $kernel_size && bootm $kernel_load" 206 #endif 207 208 /* Monitor Command Prompt */ 209 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 210 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 211 212 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 213 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 214 #define CONFIG_SPL_MAX_SIZE 0x16000 215 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 216 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 217 #define CONFIG_SPL_TEXT_BASE 0x1800a000 218 219 #ifdef CONFIG_NAND_BOOT 220 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 221 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 222 #endif 223 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 224 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 225 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 226 227 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 228 229 #include <asm/arch/soc.h> 230 231 #endif /* __LS2_COMMON_H */ 232