1 /* 2 * Copyright 2017 NXP 3 * Copyright (C) 2014 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __LS2_COMMON_H 9 #define __LS2_COMMON_H 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_MP 14 #define CONFIG_GICV3 15 #define CONFIG_FSL_TZPC_BP147 16 17 #include <asm/arch/stream_id_lsch3.h> 18 #include <asm/arch/config.h> 19 20 /* Link Definitions */ 21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 22 23 /* We need architecture specific misc initializations */ 24 25 /* Link Definitions */ 26 #ifndef CONFIG_QSPI_BOOT 27 #else 28 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 29 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 30 #define CONFIG_ENV_SECT_SIZE 0x40000 31 #endif 32 33 #define CONFIG_SKIP_LOWLEVEL_INIT 34 35 #ifndef CONFIG_SPL 36 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 37 #endif 38 #ifndef CONFIG_SYS_FSL_DDR4 39 #define CONFIG_SYS_DDR_RAW_TIMING 40 #endif 41 42 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 49 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 50 51 /* 52 * SMP Definitinos 53 */ 54 #define CPU_RELEASE_ADDR secondary_boot_func 55 56 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 58 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 59 /* 60 * DDR controller use 0 as the base address for binding. 61 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 62 */ 63 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 64 #define CONFIG_DP_DDR_CTRL 2 65 #define CONFIG_DP_DDR_NUM_CTRLS 1 66 #endif 67 68 /* Generic Timer Definitions */ 69 /* 70 * This is not an accurate number. It is used in start.S. The frequency 71 * will be udpated later when get_bus_freq(0) is available. 72 */ 73 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 74 75 /* Size of malloc() pool */ 76 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 81 /* Serial Port */ 82 #define CONFIG_CONS_INDEX 1 83 #define CONFIG_SYS_NS16550_SERIAL 84 #define CONFIG_SYS_NS16550_REG_SIZE 1 85 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 86 87 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 88 89 /* IFC */ 90 #define CONFIG_FSL_IFC 91 92 /* 93 * During booting, IFC is mapped at the region of 0x30000000. 94 * But this region is limited to 256MB. To accommodate NOR, promjet 95 * and FPGA. This region is divided as below: 96 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 97 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 98 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 99 * 100 * To accommodate bigger NOR flash and other devices, we will map IFC 101 * chip selects to as below: 102 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 103 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 104 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 105 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 106 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 107 * 108 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 109 * CONFIG_SYS_FLASH_BASE has the final address (core view) 110 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 111 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 112 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 113 */ 114 115 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 116 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 117 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 118 119 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 120 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 121 122 #ifndef __ASSEMBLY__ 123 unsigned long long get_qixis_addr(void); 124 #endif 125 #define QIXIS_BASE get_qixis_addr() 126 #define QIXIS_BASE_PHYS 0x20000000 127 #define QIXIS_BASE_PHYS_EARLY 0xC000000 128 #define QIXIS_STAT_PRES1 0xb 129 #define QIXIS_SDID_MASK 0x07 130 #define QIXIS_ESDHC_NO_ADAPTER 0x7 131 132 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 133 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 134 135 /* MC firmware */ 136 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 137 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 138 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 139 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 140 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 141 /* For LS2085A */ 142 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 143 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 144 145 /* Define phy_reset function to boot the MC based on mcinitcmd. 146 * This happens late enough to properly fixup u-boot env MAC addresses. 147 */ 148 #define CONFIG_RESET_PHY_R 149 150 /* 151 * Carve out a DDR region which will not be used by u-boot/Linux 152 * 153 * It will be used by MC and Debug Server. The MC region must be 154 * 512MB aligned, so the min size to hide is 512MB. 155 */ 156 #ifdef CONFIG_FSL_MC_ENET 157 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 158 #endif 159 160 /* Command line configuration */ 161 162 /* Miscellaneous configurable options */ 163 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 164 165 /* Physical Memory Map */ 166 /* fixme: these need to be checked against the board */ 167 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 168 169 #define CONFIG_NR_DRAM_BANKS 3 170 171 #define CONFIG_HWCONFIG 172 #define HWCONFIG_BUFFER_SIZE 128 173 174 /* Allow to overwrite serial and ethaddr */ 175 #define CONFIG_ENV_OVERWRITE 176 177 /* Initial environment variables */ 178 #define CONFIG_EXTRA_ENV_SETTINGS \ 179 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 180 "loadaddr=0x80100000\0" \ 181 "kernel_addr=0x100000\0" \ 182 "ramdisk_addr=0x800000\0" \ 183 "ramdisk_size=0x2000000\0" \ 184 "fdt_high=0xa0000000\0" \ 185 "initrd_high=0xffffffffffffffff\0" \ 186 "kernel_start=0x581000000\0" \ 187 "kernel_load=0xa0000000\0" \ 188 "kernel_size=0x2800000\0" \ 189 "console=ttyAMA0,38400n8\0" \ 190 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 191 " 0x580e00000 \0" 192 193 #ifdef CONFIG_SD_BOOT 194 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 195 " fsl_mc apply dpl 0x80200000 &&" \ 196 " mmc read $kernel_load $kernel_start" \ 197 " $kernel_size && bootm $kernel_load" 198 #else 199 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 200 " cp.b $kernel_start $kernel_load" \ 201 " $kernel_size && bootm $kernel_load" 202 #endif 203 204 /* Monitor Command Prompt */ 205 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 206 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 207 208 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 209 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 210 #define CONFIG_SPL_MAX_SIZE 0x16000 211 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 212 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 213 #define CONFIG_SPL_TEXT_BASE 0x1800a000 214 215 #ifdef CONFIG_NAND_BOOT 216 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 217 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 218 #endif 219 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 220 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 221 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 222 223 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 224 225 #include <asm/arch/soc.h> 226 227 #endif /* __LS2_COMMON_H */ 228