1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_MP 13 #define CONFIG_GICV3 14 #define CONFIG_FSL_TZPC_BP147 15 16 #include <asm/arch/ls2080a_stream_id.h> 17 #include <asm/arch/config.h> 18 19 /* Link Definitions */ 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 22 /* We need architecture specific misc initializations */ 23 24 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 25 26 /* Link Definitions */ 27 #ifndef CONFIG_QSPI_BOOT 28 #ifdef CONFIG_SPL 29 #define CONFIG_SYS_TEXT_BASE 0x80400000 30 #else 31 #define CONFIG_SYS_TEXT_BASE 0x30100000 32 #endif 33 #endif 34 35 #define CONFIG_SUPPORT_RAW_INITRD 36 37 #define CONFIG_SKIP_LOWLEVEL_INIT 38 39 #ifndef CONFIG_SPL 40 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 41 #endif 42 #ifndef CONFIG_SYS_FSL_DDR4 43 #define CONFIG_SYS_DDR_RAW_TIMING 44 #endif 45 46 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 47 48 #define CONFIG_VERY_BIG_RAM 49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 50 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 52 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 53 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 54 55 /* 56 * SMP Definitinos 57 */ 58 #define CPU_RELEASE_ADDR secondary_boot_func 59 60 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 61 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 62 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 63 /* 64 * DDR controller use 0 as the base address for binding. 65 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 66 */ 67 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 68 #define CONFIG_DP_DDR_CTRL 2 69 #define CONFIG_DP_DDR_NUM_CTRLS 1 70 #endif 71 72 /* Generic Timer Definitions */ 73 /* 74 * This is not an accurate number. It is used in start.S. The frequency 75 * will be udpated later when get_bus_freq(0) is available. 76 */ 77 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 78 79 /* Size of malloc() pool */ 80 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 81 82 /* I2C */ 83 #define CONFIG_SYS_I2C 84 #define CONFIG_SYS_I2C_MXC 85 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 86 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 87 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 88 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 89 90 /* Serial Port */ 91 #define CONFIG_CONS_INDEX 1 92 #define CONFIG_SYS_NS16550_SERIAL 93 #define CONFIG_SYS_NS16550_REG_SIZE 1 94 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 95 96 #define CONFIG_BAUDRATE 115200 97 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 98 99 /* IFC */ 100 #define CONFIG_FSL_IFC 101 102 /* 103 * During booting, IFC is mapped at the region of 0x30000000. 104 * But this region is limited to 256MB. To accommodate NOR, promjet 105 * and FPGA. This region is divided as below: 106 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 107 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 108 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 109 * 110 * To accommodate bigger NOR flash and other devices, we will map IFC 111 * chip selects to as below: 112 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 113 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 114 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 115 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 116 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 117 * 118 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 119 * CONFIG_SYS_FLASH_BASE has the final address (core view) 120 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 121 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 122 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 123 */ 124 125 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 126 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 127 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 128 129 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 130 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 131 132 #ifndef __ASSEMBLY__ 133 unsigned long long get_qixis_addr(void); 134 #endif 135 #define QIXIS_BASE get_qixis_addr() 136 #define QIXIS_BASE_PHYS 0x20000000 137 #define QIXIS_BASE_PHYS_EARLY 0xC000000 138 #define QIXIS_STAT_PRES1 0xb 139 #define QIXIS_SDID_MASK 0x07 140 #define QIXIS_ESDHC_NO_ADAPTER 0x7 141 142 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 143 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 144 145 /* MC firmware */ 146 #define CONFIG_FSL_MC_ENET 147 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 148 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 149 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 150 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 151 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 152 /* For LS2085A */ 153 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 154 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 155 156 /* 157 * Carve out a DDR region which will not be used by u-boot/Linux 158 * 159 * It will be used by MC and Debug Server. The MC region must be 160 * 512MB aligned, so the min size to hide is 512MB. 161 */ 162 #ifdef CONFIG_FSL_MC_ENET 163 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 164 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 165 #endif 166 167 /* Command line configuration */ 168 #define CONFIG_CMD_ENV 169 170 /* Miscellaneous configurable options */ 171 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 172 173 /* Physical Memory Map */ 174 /* fixme: these need to be checked against the board */ 175 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 176 177 #define CONFIG_NR_DRAM_BANKS 3 178 179 #define CONFIG_HWCONFIG 180 #define HWCONFIG_BUFFER_SIZE 128 181 182 /* Allow to overwrite serial and ethaddr */ 183 #define CONFIG_ENV_OVERWRITE 184 185 /* Initial environment variables */ 186 #define CONFIG_EXTRA_ENV_SETTINGS \ 187 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 188 "loadaddr=0x80100000\0" \ 189 "kernel_addr=0x100000\0" \ 190 "ramdisk_addr=0x800000\0" \ 191 "ramdisk_size=0x2000000\0" \ 192 "fdt_high=0xa0000000\0" \ 193 "initrd_high=0xffffffffffffffff\0" \ 194 "kernel_start=0x581200000\0" \ 195 "kernel_load=0xa0000000\0" \ 196 "kernel_size=0x2800000\0" \ 197 "console=ttyAMA0,38400n8\0" \ 198 "mcinitcmd=fsl_mc start mc 0x580300000" \ 199 " 0x580800000 \0" 200 201 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 202 "earlycon=uart8250,mmio,0x21c0500 " \ 203 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 204 " hugepagesz=2m hugepages=256" 205 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ 206 " cp.b $kernel_start $kernel_load" \ 207 " $kernel_size && bootm $kernel_load" 208 209 /* Monitor Command Prompt */ 210 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 212 sizeof(CONFIG_SYS_PROMPT) + 16) 213 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 214 #define CONFIG_SYS_LONGHELP 215 #define CONFIG_CMDLINE_EDITING 1 216 #define CONFIG_AUTO_COMPLETE 217 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 218 219 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 220 221 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 222 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 223 #define CONFIG_SPL_FRAMEWORK 224 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 225 #define CONFIG_SPL_MAX_SIZE 0x16000 226 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 227 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 228 #define CONFIG_SPL_TEXT_BASE 0x1800a000 229 230 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 231 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 232 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 233 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 234 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) 235 236 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 237 238 /* Hash command with SHA acceleration supported in hardware */ 239 #ifdef CONFIG_FSL_CAAM 240 #define CONFIG_CMD_HASH 241 #define CONFIG_SHA_HW_ACCEL 242 #endif 243 244 #endif /* __LS2_COMMON_H */ 245