1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_GICV3 13 #define CONFIG_FSL_TZPC_BP147 14 15 #include <asm/arch/stream_id_lsch3.h> 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 21 /* We need architecture specific misc initializations */ 22 23 /* Link Definitions */ 24 #ifndef CONFIG_QSPI_BOOT 25 #else 26 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 27 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 28 #define CONFIG_ENV_SECT_SIZE 0x40000 29 #endif 30 31 #define CONFIG_SKIP_LOWLEVEL_INIT 32 33 #ifndef CONFIG_SPL 34 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 35 #endif 36 #ifndef CONFIG_SYS_FSL_DDR4 37 #define CONFIG_SYS_DDR_RAW_TIMING 38 #endif 39 40 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 47 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 48 49 /* 50 * SMP Definitinos 51 */ 52 #define CPU_RELEASE_ADDR secondary_boot_func 53 54 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 55 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 56 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 57 /* 58 * DDR controller use 0 as the base address for binding. 59 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 60 */ 61 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 62 #define CONFIG_DP_DDR_CTRL 2 63 #define CONFIG_DP_DDR_NUM_CTRLS 1 64 #endif 65 66 /* Generic Timer Definitions */ 67 /* 68 * This is not an accurate number. It is used in start.S. The frequency 69 * will be udpated later when get_bus_freq(0) is available. 70 */ 71 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 72 73 /* Size of malloc() pool */ 74 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 75 76 /* I2C */ 77 #define CONFIG_SYS_I2C 78 79 /* Serial Port */ 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE 1 82 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 83 84 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 85 86 /* IFC */ 87 #define CONFIG_FSL_IFC 88 89 /* 90 * During booting, IFC is mapped at the region of 0x30000000. 91 * But this region is limited to 256MB. To accommodate NOR, promjet 92 * and FPGA. This region is divided as below: 93 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 94 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 95 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 96 * 97 * To accommodate bigger NOR flash and other devices, we will map IFC 98 * chip selects to as below: 99 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 100 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 101 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 102 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 103 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 104 * 105 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 106 * CONFIG_SYS_FLASH_BASE has the final address (core view) 107 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 108 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 109 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 110 */ 111 112 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 113 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 114 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 115 116 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 117 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 118 119 #ifndef __ASSEMBLY__ 120 unsigned long long get_qixis_addr(void); 121 #endif 122 #define QIXIS_BASE get_qixis_addr() 123 #define QIXIS_BASE_PHYS 0x20000000 124 #define QIXIS_BASE_PHYS_EARLY 0xC000000 125 #define QIXIS_STAT_PRES1 0xb 126 #define QIXIS_SDID_MASK 0x07 127 #define QIXIS_ESDHC_NO_ADAPTER 0x7 128 129 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 130 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 131 132 /* MC firmware */ 133 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 134 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 135 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 136 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 137 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 138 /* For LS2085A */ 139 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 140 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 141 142 /* Define phy_reset function to boot the MC based on mcinitcmd. 143 * This happens late enough to properly fixup u-boot env MAC addresses. 144 */ 145 #define CONFIG_RESET_PHY_R 146 147 /* 148 * Carve out a DDR region which will not be used by u-boot/Linux 149 * 150 * It will be used by MC and Debug Server. The MC region must be 151 * 512MB aligned, so the min size to hide is 512MB. 152 */ 153 #ifdef CONFIG_FSL_MC_ENET 154 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 155 #endif 156 157 /* Command line configuration */ 158 159 /* Miscellaneous configurable options */ 160 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 161 162 /* Physical Memory Map */ 163 /* fixme: these need to be checked against the board */ 164 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 165 166 #define CONFIG_HWCONFIG 167 #define HWCONFIG_BUFFER_SIZE 128 168 169 /* Allow to overwrite serial and ethaddr */ 170 #define CONFIG_ENV_OVERWRITE 171 172 /* Initial environment variables */ 173 #define CONFIG_EXTRA_ENV_SETTINGS \ 174 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 175 "loadaddr=0x80100000\0" \ 176 "kernel_addr=0x100000\0" \ 177 "ramdisk_addr=0x800000\0" \ 178 "ramdisk_size=0x2000000\0" \ 179 "fdt_high=0xa0000000\0" \ 180 "initrd_high=0xffffffffffffffff\0" \ 181 "kernel_start=0x581000000\0" \ 182 "kernel_load=0xa0000000\0" \ 183 "kernel_size=0x2800000\0" \ 184 "console=ttyAMA0,38400n8\0" \ 185 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 186 " 0x580e00000 \0" 187 188 #ifdef CONFIG_SD_BOOT 189 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 190 " fsl_mc apply dpl 0x80200000 &&" \ 191 " mmc read $kernel_load $kernel_start" \ 192 " $kernel_size && bootm $kernel_load" 193 #else 194 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 195 " cp.b $kernel_start $kernel_load" \ 196 " $kernel_size && bootm $kernel_load" 197 #endif 198 199 /* Monitor Command Prompt */ 200 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 201 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 202 203 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 204 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 205 #define CONFIG_SPL_MAX_SIZE 0x16000 206 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 207 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 208 #define CONFIG_SPL_TEXT_BASE 0x1800a000 209 210 #ifdef CONFIG_NAND_BOOT 211 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 212 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 213 #endif 214 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 215 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 216 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 217 218 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 219 220 #include <asm/arch/soc.h> 221 222 #endif /* __LS2_COMMON_H */ 223