1 /*
2  * Copyright (C) 2014 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS2_COMMON_H
8 #define __LS2_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_MP
13 #define CONFIG_GICV3
14 #define CONFIG_FSL_TZPC_BP147
15 
16 #include <asm/arch/ls2080a_stream_id.h>
17 #include <asm/arch/config.h>
18 
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
21 
22 /* We need architecture specific misc initializations */
23 #define CONFIG_ARCH_MISC_INIT
24 
25 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
26 
27 /* Link Definitions */
28 #ifndef CONFIG_QSPI_BOOT
29 #ifdef CONFIG_SPL
30 #define CONFIG_SYS_TEXT_BASE		0x80400000
31 #else
32 #define CONFIG_SYS_TEXT_BASE		0x30100000
33 #endif
34 #endif
35 
36 #ifdef CONFIG_EMU
37 #define CONFIG_SYS_NO_FLASH
38 #endif
39 
40 #define CONFIG_SUPPORT_RAW_INITRD
41 
42 #define CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_BOARD_EARLY_INIT_F	1
44 
45 #ifndef CONFIG_SPL
46 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
47 #endif
48 #ifndef CONFIG_SYS_FSL_DDR4
49 #define CONFIG_SYS_DDR_RAW_TIMING
50 #endif
51 
52 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
53 
54 #define CONFIG_VERY_BIG_RAM
55 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
56 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
57 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
58 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
59 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
60 
61 /*
62  * SMP Definitinos
63  */
64 #define CPU_RELEASE_ADDR		secondary_boot_func
65 
66 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
67 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
68 #define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
69 /*
70  * DDR controller use 0 as the base address for binding.
71  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
72  */
73 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
74 #define CONFIG_DP_DDR_CTRL		2
75 #define CONFIG_DP_DDR_NUM_CTRLS		1
76 #endif
77 
78 /* Generic Timer Definitions */
79 /*
80  * This is not an accurate number. It is used in start.S. The frequency
81  * will be udpated later when get_bus_freq(0) is available.
82  */
83 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
84 
85 /* Size of malloc() pool */
86 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
87 
88 /* I2C */
89 #define CONFIG_SYS_I2C
90 #define CONFIG_SYS_I2C_MXC
91 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
92 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
93 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
94 #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
95 
96 /* Serial Port */
97 #define CONFIG_CONS_INDEX       1
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_REG_SIZE     1
100 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
101 
102 #define CONFIG_BAUDRATE			115200
103 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
104 
105 /* IFC */
106 #define CONFIG_FSL_IFC
107 
108 /*
109  * During booting, IFC is mapped at the region of 0x30000000.
110  * But this region is limited to 256MB. To accommodate NOR, promjet
111  * and FPGA. This region is divided as below:
112  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
113  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
114  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
115  *
116  * To accommodate bigger NOR flash and other devices, we will map IFC
117  * chip selects to as below:
118  * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
119  * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
120  * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
121  * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
122  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
123  *
124  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
125  * CONFIG_SYS_FLASH_BASE has the final address (core view)
126  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
127  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
128  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
129  */
130 
131 #define CONFIG_SYS_FLASH_BASE			0x580000000ULL
132 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
133 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
134 
135 #define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
136 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
137 
138 #ifndef __ASSEMBLY__
139 unsigned long long get_qixis_addr(void);
140 #endif
141 #define QIXIS_BASE				get_qixis_addr()
142 #define QIXIS_BASE_PHYS				0x20000000
143 #define QIXIS_BASE_PHYS_EARLY			0xC000000
144 #define QIXIS_STAT_PRES1			0xb
145 #define QIXIS_SDID_MASK				0x07
146 #define QIXIS_ESDHC_NO_ADAPTER			0x7
147 
148 #define CONFIG_SYS_NAND_BASE			0x530000000ULL
149 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
150 
151 /* MC firmware */
152 #define CONFIG_FSL_MC_ENET
153 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
154 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
155 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
156 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
157 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
158 /* For LS2085A */
159 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
160 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
161 
162 /*
163  * Carve out a DDR region which will not be used by u-boot/Linux
164  *
165  * It will be used by MC and Debug Server. The MC region must be
166  * 512MB aligned, so the min size to hide is 512MB.
167  */
168 #ifdef CONFIG_FSL_MC_ENET
169 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
170 #define CONFIG_SYS_MC_RSV_MEM_ALIGN			(512UL * 1024 * 1024)
171 #endif
172 
173 /* Command line configuration */
174 #define CONFIG_CMD_ENV
175 
176 /* Miscellaneous configurable options */
177 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
178 #define CONFIG_ARCH_EARLY_INIT_R
179 
180 /* Physical Memory Map */
181 /* fixme: these need to be checked against the board */
182 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
183 
184 #define CONFIG_NR_DRAM_BANKS		3
185 
186 #define CONFIG_HWCONFIG
187 #define HWCONFIG_BUFFER_SIZE		128
188 
189 /* Allow to overwrite serial and ethaddr */
190 #define CONFIG_ENV_OVERWRITE
191 
192 /* Initial environment variables */
193 #define CONFIG_EXTRA_ENV_SETTINGS		\
194 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
195 	"loadaddr=0x80100000\0"			\
196 	"kernel_addr=0x100000\0"		\
197 	"ramdisk_addr=0x800000\0"		\
198 	"ramdisk_size=0x2000000\0"		\
199 	"fdt_high=0xa0000000\0"			\
200 	"initrd_high=0xffffffffffffffff\0"	\
201 	"kernel_start=0x581200000\0"		\
202 	"kernel_load=0xa0000000\0"		\
203 	"kernel_size=0x2800000\0"		\
204 	"console=ttyAMA0,38400n8\0"		\
205 	"mcinitcmd=fsl_mc start mc 0x580300000"	\
206 	" 0x580800000 \0"
207 
208 #define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
209 				"earlycon=uart8250,mmio,0x21c0500 " \
210 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
211 				" hugepagesz=2m hugepages=256"
212 #define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
213 				" cp.b $kernel_start $kernel_load" \
214 				" $kernel_size && bootm $kernel_load"
215 
216 /* Monitor Command Prompt */
217 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
218 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
219 					sizeof(CONFIG_SYS_PROMPT) + 16)
220 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
221 #define CONFIG_SYS_LONGHELP
222 #define CONFIG_CMDLINE_EDITING		1
223 #define CONFIG_AUTO_COMPLETE
224 #define CONFIG_SYS_MAXARGS		64	/* max command args */
225 
226 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
227 
228 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
229 #define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
230 #define CONFIG_SPL_FRAMEWORK
231 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
232 #define CONFIG_SPL_MAX_SIZE		0x16000
233 #define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
234 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
235 #define CONFIG_SPL_TEXT_BASE		0x1800a000
236 
237 #define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
238 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
239 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
240 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
241 #define CONFIG_SYS_MONITOR_LEN		(640 * 1024)
242 
243 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
244 
245 /* Hash command with SHA acceleration supported in hardware */
246 #ifdef CONFIG_FSL_CAAM
247 #define CONFIG_CMD_HASH
248 #define CONFIG_SHA_HW_ACCEL
249 #endif
250 
251 #endif /* __LS2_COMMON_H */
252