1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #ifndef SPL_NO_BOARDINFO 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 #endif 15 16 #define CONFIG_MISC_INIT_R 17 18 #if defined(CONFIG_QSPI_BOOT) 19 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 20 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 21 #define CONFIG_ENV_SECT_SIZE 0x40000 22 #elif defined(CONFIG_SD_BOOT) 23 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 24 #define CONFIG_SYS_MMC_ENV_DEV 0 25 #define CONFIG_ENV_SIZE 0x2000 26 #else 27 #define CONFIG_ENV_IS_IN_FLASH 28 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 29 #define CONFIG_ENV_SECT_SIZE 0x20000 30 #define CONFIG_ENV_SIZE 0x20000 31 #endif 32 33 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 34 #ifndef CONFIG_SPL_BUILD 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #endif 37 #define SYS_NO_FLASH 38 #undef CONFIG_CMD_IMLS 39 #endif 40 41 #define CONFIG_SYS_CLK_FREQ 100000000 42 #define CONFIG_DDR_CLK_FREQ 100000000 43 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 44 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 46 #define CONFIG_DDR_SPD 47 #ifdef CONFIG_EMU 48 #define CONFIG_SYS_FSL_DDR_EMU 49 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 50 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 51 #else 52 #define CONFIG_DDR_ECC 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 54 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 55 #endif 56 #define SPD_EEPROM_ADDRESS 0x51 57 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 60 61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 65 66 #define CONFIG_SYS_NOR0_CSPR \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 73 CSPR_PORT_SIZE_16 | \ 74 CSPR_MSEL_NOR | \ 75 CSPR_V) 76 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 77 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 78 FTIM0_NOR_TEADC(0x1) | \ 79 FTIM0_NOR_TEAHC(0x1)) 80 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 81 FTIM1_NOR_TRAD_NOR(0x1)) 82 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 83 FTIM2_NOR_TCH(0x0) | \ 84 FTIM2_NOR_TWP(0x1)) 85 #define CONFIG_SYS_NOR_FTIM3 0x04000000 86 #define CONFIG_SYS_IFC_CCR 0x01000000 87 88 #ifndef SYS_NO_FLASH 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 #define CONFIG_SYS_FLASH_QUIET_TEST 93 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 94 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 96 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 97 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 98 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 99 100 #define CONFIG_SYS_FLASH_EMPTY_INFO 101 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 102 #endif 103 #endif 104 105 #ifndef SPL_NO_IFC 106 #define CONFIG_NAND_FSL_IFC 107 #endif 108 109 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 110 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 111 112 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 113 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 114 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 115 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 116 | CSPR_V) 117 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 118 119 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 120 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 121 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 122 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 123 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 124 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 125 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 126 127 #define CONFIG_SYS_NAND_ONFI_DETECTION 128 129 /* ONFI NAND Flash mode0 Timing Params */ 130 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 131 FTIM0_NAND_TWP(0x18) | \ 132 FTIM0_NAND_TWCHT(0x07) | \ 133 FTIM0_NAND_TWH(0x0a)) 134 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 135 FTIM1_NAND_TWBE(0x39) | \ 136 FTIM1_NAND_TRR(0x0e) | \ 137 FTIM1_NAND_TRP(0x18)) 138 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 139 FTIM2_NAND_TREH(0x0a) | \ 140 FTIM2_NAND_TWHRE(0x1e)) 141 #define CONFIG_SYS_NAND_FTIM3 0x0 142 143 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 145 #define CONFIG_MTD_NAND_VERIFY_WRITE 146 #define CONFIG_CMD_NAND 147 148 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 149 150 #ifndef SPL_NO_QIXIS 151 #define CONFIG_FSL_QIXIS 152 #endif 153 154 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 155 #define QIXIS_LBMAP_SWITCH 2 156 #define QIXIS_QMAP_MASK 0xe0 157 #define QIXIS_QMAP_SHIFT 5 158 #define QIXIS_LBMAP_MASK 0x1f 159 #define QIXIS_LBMAP_SHIFT 5 160 #define QIXIS_LBMAP_DFLTBANK 0x00 161 #define QIXIS_LBMAP_ALTBANK 0x20 162 #define QIXIS_LBMAP_SD 0x00 163 #define QIXIS_LBMAP_SD_QSPI 0x00 164 #define QIXIS_LBMAP_QSPI 0x00 165 #define QIXIS_RCW_SRC_SD 0x40 166 #define QIXIS_RCW_SRC_QSPI 0x62 167 #define QIXIS_RST_CTL_RESET 0x31 168 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 169 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 170 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 171 #define QIXIS_RST_FORCE_MEM 0x01 172 173 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 174 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 175 | CSPR_PORT_SIZE_8 \ 176 | CSPR_MSEL_GPCM \ 177 | CSPR_V) 178 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 179 | CSPR_PORT_SIZE_8 \ 180 | CSPR_MSEL_GPCM \ 181 | CSPR_V) 182 183 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 184 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 185 /* QIXIS Timing parameters*/ 186 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 187 FTIM0_GPCM_TEADC(0x0e) | \ 188 FTIM0_GPCM_TEAHC(0x0e)) 189 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 190 FTIM1_GPCM_TRAD(0x3f)) 191 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 192 FTIM2_GPCM_TCH(0xf) | \ 193 FTIM2_GPCM_TWP(0x3E)) 194 #define SYS_FPGA_CS_FTIM3 0x0 195 196 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 197 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 198 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 199 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 200 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 201 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 202 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 203 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 204 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 205 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 206 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 207 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 208 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 209 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 210 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 211 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 212 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 213 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 214 #else 215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 217 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 224 #endif 225 226 227 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 228 229 /* 230 * I2C bus multiplexer 231 */ 232 #define I2C_MUX_PCA_ADDR_PRI 0x77 233 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 234 #define I2C_RETIMER_ADDR 0x18 235 #define I2C_MUX_CH_DEFAULT 0x8 236 #define I2C_MUX_CH5 0xD 237 238 #ifndef SPL_NO_RTC 239 /* 240 * RTC configuration 241 */ 242 #define RTC 243 #define CONFIG_RTC_PCF8563 1 244 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 245 #define CONFIG_CMD_DATE 246 #endif 247 248 /* EEPROM */ 249 #define CONFIG_ID_EEPROM 250 #define CONFIG_SYS_I2C_EEPROM_NXID 251 #define CONFIG_SYS_EEPROM_BUS_NUM 0 252 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 256 257 #ifndef SPL_NO_QSPI 258 /* QSPI device */ 259 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 260 #define CONFIG_FSL_QSPI 261 #define FSL_QSPI_FLASH_SIZE (1 << 26) 262 #define FSL_QSPI_FLASH_NUM 2 263 #endif 264 #endif 265 266 #define CONFIG_CMD_MEMINFO 267 #define CONFIG_CMD_MEMTEST 268 #define CONFIG_SYS_MEMTEST_START 0x80000000 269 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 270 271 #ifdef CONFIG_SPL_BUILD 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 273 #else 274 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 275 #endif 276 277 #define CONFIG_FSL_MEMAC 278 279 #ifndef SPL_NO_ENV 280 /* Initial environment variables */ 281 #if defined(CONFIG_QSPI_BOOT) 282 #define MC_INIT_CMD \ 283 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 284 "sf read 0x80100000 0xE00000 0x100000;" \ 285 "env exists secureboot && " \ 286 "sf read 0x80700000 0x700000 0x40000 && " \ 287 "sf read 0x80740000 0x740000 0x40000 && " \ 288 "esbc_validate 0x80700000 && " \ 289 "esbc_validate 0x80740000 ;" \ 290 "fsl_mc start mc 0x80000000 0x80100000\0" \ 291 "mcmemsize=0x70000000\0" 292 #elif defined(CONFIG_SD_BOOT) 293 #define MC_INIT_CMD \ 294 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 295 "mmc read 0x80100000 0x7000 0x800;" \ 296 "env exists secureboot && " \ 297 "mmc read 0x80700000 0x3800 0x10 && " \ 298 "mmc read 0x80740000 0x3A00 0x10 && " \ 299 "esbc_validate 0x80700000 && " \ 300 "esbc_validate 0x80740000 ;" \ 301 "fsl_mc start mc 0x80000000 0x80100000\0" \ 302 "mcmemsize=0x70000000\0" 303 #endif 304 305 #undef CONFIG_EXTRA_ENV_SETTINGS 306 #define CONFIG_EXTRA_ENV_SETTINGS \ 307 "BOARD=ls1088ardb\0" \ 308 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 309 "ramdisk_addr=0x800000\0" \ 310 "ramdisk_size=0x2000000\0" \ 311 "fdt_high=0xa0000000\0" \ 312 "initrd_high=0xffffffffffffffff\0" \ 313 "fdt_addr=0x64f00000\0" \ 314 "kernel_addr=0x1000000\0" \ 315 "kernel_addr_sd=0x8000\0" \ 316 "kernelhdr_addr_sd=0x4000\0" \ 317 "kernel_start=0x580100000\0" \ 318 "kernelheader_start=0x580800000\0" \ 319 "scriptaddr=0x80000000\0" \ 320 "scripthdraddr=0x80080000\0" \ 321 "fdtheader_addr_r=0x80100000\0" \ 322 "kernelheader_addr=0x800000\0" \ 323 "kernelheader_addr_r=0x80200000\0" \ 324 "kernel_addr_r=0x81000000\0" \ 325 "kernelheader_size=0x40000\0" \ 326 "fdt_addr_r=0x90000000\0" \ 327 "load_addr=0xa0000000\0" \ 328 "kernel_size=0x2800000\0" \ 329 "kernel_size_sd=0x14000\0" \ 330 "kernelhdr_size_sd=0x10\0" \ 331 MC_INIT_CMD \ 332 BOOTENV \ 333 "boot_scripts=ls1088ardb_boot.scr\0" \ 334 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 335 "scan_dev_for_boot_part=" \ 336 "part list ${devtype} ${devnum} devplist; " \ 337 "env exists devplist || setenv devplist 1; " \ 338 "for distro_bootpart in ${devplist}; do " \ 339 "if fstype ${devtype} " \ 340 "${devnum}:${distro_bootpart} " \ 341 "bootfstype; then " \ 342 "run scan_dev_for_boot; " \ 343 "fi; " \ 344 "done\0" \ 345 "scan_dev_for_boot=" \ 346 "echo Scanning ${devtype} " \ 347 "${devnum}:${distro_bootpart}...; " \ 348 "for prefix in ${boot_prefixes}; do " \ 349 "run scan_dev_for_scripts; " \ 350 "done;\0" \ 351 "boot_a_script=" \ 352 "load ${devtype} ${devnum}:${distro_bootpart} " \ 353 "${scriptaddr} ${prefix}${script}; " \ 354 "env exists secureboot && load ${devtype} " \ 355 "${devnum}:${distro_bootpart} " \ 356 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 357 "&& esbc_validate ${scripthdraddr};" \ 358 "source ${scriptaddr}\0" \ 359 "installer=load mmc 0:2 $load_addr " \ 360 "/flex_installer_arm64.itb; " \ 361 "env exists mcinitcmd && run mcinitcmd && " \ 362 "mmc read 0x80200000 0x6800 0x800;" \ 363 "fsl_mc apply dpl 0x80200000;" \ 364 "bootm $load_addr#ls1088ardb\0" \ 365 "qspi_bootcmd=echo Trying load from qspi..;" \ 366 "sf probe && sf read $load_addr " \ 367 "$kernel_addr $kernel_size ; env exists secureboot " \ 368 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 369 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 370 "bootm $load_addr#$BOARD\0" \ 371 "sd_bootcmd=echo Trying load from sd card..;" \ 372 "mmcinfo; mmc read $load_addr " \ 373 "$kernel_addr_sd $kernel_size_sd ;" \ 374 "env exists secureboot && mmc read $kernelheader_addr_r "\ 375 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 376 " && esbc_validate ${kernelheader_addr_r};" \ 377 "bootm $load_addr#$BOARD\0" 378 379 #undef CONFIG_BOOTCOMMAND 380 #if defined(CONFIG_QSPI_BOOT) 381 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 382 #define CONFIG_BOOTCOMMAND \ 383 "sf read 0x80200000 0xd00000 0x100000;" \ 384 "env exists mcinitcmd && env exists secureboot " \ 385 " && sf read 0x80780000 0x780000 0x100000 " \ 386 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 387 "&& fsl_mc apply dpl 0x80200000;" \ 388 "run distro_bootcmd;run qspi_bootcmd;" \ 389 "env exists secureboot && esbc_halt;" 390 391 /* Try to boot an on-SD kernel first, then do normal distro boot */ 392 #elif defined(CONFIG_SD_BOOT) 393 #define CONFIG_BOOTCOMMAND \ 394 "env exists mcinitcmd && mmcinfo; " \ 395 "mmc read 0x80200000 0x6800 0x800; " \ 396 "env exists mcinitcmd && env exists secureboot " \ 397 " && mmc read 0x80780000 0x3800 0x10 " \ 398 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 399 "&& fsl_mc apply dpl 0x80200000;" \ 400 "run distro_bootcmd;run sd_bootcmd;" \ 401 "env exists secureboot && esbc_halt;" 402 #endif 403 404 /* MAC/PHY configuration */ 405 #ifdef CONFIG_FSL_MC_ENET 406 #define CONFIG_PHYLIB_10G 407 #define CONFIG_PHY_GIGE 408 #define CONFIG_PHYLIB 409 410 #define CONFIG_PHY_VITESSE 411 #define CONFIG_PHY_AQUANTIA 412 #define AQ_PHY_ADDR1 0x00 413 #define AQR105_IRQ_MASK 0x00000004 414 415 #define QSGMII1_PORT1_PHY_ADDR 0x0c 416 #define QSGMII1_PORT2_PHY_ADDR 0x0d 417 #define QSGMII1_PORT3_PHY_ADDR 0x0e 418 #define QSGMII1_PORT4_PHY_ADDR 0x0f 419 #define QSGMII2_PORT1_PHY_ADDR 0x1c 420 #define QSGMII2_PORT2_PHY_ADDR 0x1d 421 #define QSGMII2_PORT3_PHY_ADDR 0x1e 422 #define QSGMII2_PORT4_PHY_ADDR 0x1f 423 424 #define CONFIG_MII 425 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 426 #define CONFIG_PHY_GIGE 427 #endif 428 #endif 429 430 /* MMC */ 431 #ifdef CONFIG_MMC 432 #define CONFIG_FSL_ESDHC 433 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 434 #endif 435 436 #ifndef SPL_NO_ENV 437 #undef CONFIG_CMDLINE_EDITING 438 #include <config_distro_defaults.h> 439 440 #define BOOT_TARGET_DEVICES(func) \ 441 func(MMC, mmc, 0) \ 442 func(SCSI, scsi, 0) \ 443 func(DHCP, dhcp, na) 444 #include <config_distro_bootcmd.h> 445 #endif 446 447 #include <asm/fsl_secure_boot.h> 448 449 #endif /* __LS1088A_RDB_H */ 450