1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO_LATE 13 14 #if defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 16 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 17 #define CONFIG_ENV_SECT_SIZE 0x40000 18 #elif defined(CONFIG_SD_BOOT) 19 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 20 #define CONFIG_SYS_MMC_ENV_DEV 0 21 #define CONFIG_ENV_SIZE 0x2000 22 #else 23 #define CONFIG_ENV_IS_IN_FLASH 24 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 25 #define CONFIG_ENV_SECT_SIZE 0x20000 26 #define CONFIG_ENV_SIZE 0x20000 27 #endif 28 29 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 30 #define CONFIG_QIXIS_I2C_ACCESS 31 #define SYS_NO_FLASH 32 #undef CONFIG_CMD_IMLS 33 #endif 34 35 #define CONFIG_SYS_CLK_FREQ 100000000 36 #define CONFIG_DDR_CLK_FREQ 100000000 37 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 38 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 39 40 #define CONFIG_DDR_SPD 41 #ifdef CONFIG_EMU 42 #define CONFIG_SYS_FSL_DDR_EMU 43 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 44 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 45 #else 46 #define CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 #define SPD_EEPROM_ADDRESS 0x51 51 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 54 55 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 56 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 57 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 58 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 59 60 #define CONFIG_SYS_NOR0_CSPR \ 61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 62 CSPR_PORT_SIZE_16 | \ 63 CSPR_MSEL_NOR | \ 64 CSPR_V) 65 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 67 CSPR_PORT_SIZE_16 | \ 68 CSPR_MSEL_NOR | \ 69 CSPR_V) 70 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 71 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 72 FTIM0_NOR_TEADC(0x1) | \ 73 FTIM0_NOR_TEAHC(0x1)) 74 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 75 FTIM1_NOR_TRAD_NOR(0x1)) 76 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 77 FTIM2_NOR_TCH(0x0) | \ 78 FTIM2_NOR_TWP(0x1)) 79 #define CONFIG_SYS_NOR_FTIM3 0x04000000 80 #define CONFIG_SYS_IFC_CCR 0x01000000 81 82 #ifndef SYS_NO_FLASH 83 #define CONFIG_FLASH_CFI_DRIVER 84 #define CONFIG_SYS_FLASH_CFI 85 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 86 #define CONFIG_SYS_FLASH_QUIET_TEST 87 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 88 89 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 90 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 91 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 92 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 93 94 #define CONFIG_SYS_FLASH_EMPTY_INFO 95 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 96 #endif 97 #endif 98 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 99 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 100 101 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 102 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 104 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 105 | CSPR_V) 106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 107 108 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 115 116 #define CONFIG_SYS_NAND_ONFI_DETECTION 117 118 /* ONFI NAND Flash mode0 Timing Params */ 119 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 120 FTIM0_NAND_TWP(0x18) | \ 121 FTIM0_NAND_TWCHT(0x07) | \ 122 FTIM0_NAND_TWH(0x0a)) 123 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 124 FTIM1_NAND_TWBE(0x39) | \ 125 FTIM1_NAND_TRR(0x0e) | \ 126 FTIM1_NAND_TRP(0x18)) 127 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 128 FTIM2_NAND_TREH(0x0a) | \ 129 FTIM2_NAND_TWHRE(0x1e)) 130 #define CONFIG_SYS_NAND_FTIM3 0x0 131 132 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 134 #define CONFIG_MTD_NAND_VERIFY_WRITE 135 136 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 137 138 #define CONFIG_FSL_QIXIS 139 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 140 #define QIXIS_LBMAP_SWITCH 2 141 #define QIXIS_QMAP_MASK 0xe0 142 #define QIXIS_QMAP_SHIFT 5 143 #define QIXIS_LBMAP_MASK 0x1f 144 #define QIXIS_LBMAP_SHIFT 5 145 #define QIXIS_LBMAP_DFLTBANK 0x00 146 #define QIXIS_LBMAP_ALTBANK 0x20 147 #define QIXIS_LBMAP_SD 0x00 148 #define QIXIS_LBMAP_SD_QSPI 0x00 149 #define QIXIS_LBMAP_QSPI 0x00 150 #define QIXIS_RCW_SRC_SD 0x40 151 #define QIXIS_RCW_SRC_QSPI 0x62 152 #define QIXIS_RST_CTL_RESET 0x31 153 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 154 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 155 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 156 #define QIXIS_RST_FORCE_MEM 0x01 157 158 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 159 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 160 | CSPR_PORT_SIZE_8 \ 161 | CSPR_MSEL_GPCM \ 162 | CSPR_V) 163 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 164 | CSPR_PORT_SIZE_8 \ 165 | CSPR_MSEL_GPCM \ 166 | CSPR_V) 167 168 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 169 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 170 /* QIXIS Timing parameters*/ 171 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 172 FTIM0_GPCM_TEADC(0x0e) | \ 173 FTIM0_GPCM_TEAHC(0x0e)) 174 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 175 FTIM1_GPCM_TRAD(0x3f)) 176 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 177 FTIM2_GPCM_TCH(0xf) | \ 178 FTIM2_GPCM_TWP(0x3E)) 179 #define SYS_FPGA_CS_FTIM3 0x0 180 181 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 182 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 183 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 184 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 185 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 186 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 187 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 188 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 189 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 190 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 191 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 192 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 193 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 194 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 195 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 196 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 197 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 198 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 199 #else 200 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 201 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 202 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 203 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 204 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 205 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 206 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 207 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 208 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 209 #endif 210 211 212 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 213 214 /* 215 * I2C bus multiplexer 216 */ 217 #define I2C_MUX_PCA_ADDR_PRI 0x77 218 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 219 #define I2C_RETIMER_ADDR 0x18 220 #define I2C_MUX_CH_DEFAULT 0x8 221 #define I2C_MUX_CH5 0xD 222 /* 223 * RTC configuration 224 */ 225 #define RTC 226 #define CONFIG_RTC_PCF8563 1 227 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 228 #define CONFIG_CMD_DATE 229 230 /* EEPROM */ 231 #define CONFIG_ID_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_NXID 233 #define CONFIG_SYS_EEPROM_BUS_NUM 0 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 238 239 /* QSPI device */ 240 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 241 #define CONFIG_FSL_QSPI 242 #define FSL_QSPI_FLASH_SIZE (1 << 26) 243 #define FSL_QSPI_FLASH_NUM 2 244 #endif 245 246 #define CONFIG_CMD_MEMINFO 247 #define CONFIG_CMD_MEMTEST 248 #define CONFIG_SYS_MEMTEST_START 0x80000000 249 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 250 251 #ifdef CONFIG_SPL_BUILD 252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 253 #else 254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 255 #endif 256 257 #define CONFIG_FSL_MEMAC 258 259 /* Initial environment variables */ 260 #if defined(CONFIG_QSPI_BOOT) 261 #define MC_INIT_CMD \ 262 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 263 "sf read 0x80100000 0xE00000 0x100000;" \ 264 "fsl_mc start mc 0x80000000 0x80100000\0" \ 265 "mcmemsize=0x70000000\0" 266 #elif defined(CONFIG_SD_BOOT) 267 #define MC_INIT_CMD \ 268 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 269 "mmc read 0x80100000 0x7000 0x800;" \ 270 "fsl_mc start mc 0x80000000 0x80100000\0" \ 271 "mcmemsize=0x70000000\0" 272 #endif 273 274 #undef CONFIG_EXTRA_ENV_SETTINGS 275 #define CONFIG_EXTRA_ENV_SETTINGS \ 276 "BOARD=ls1088ardb\0" \ 277 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 278 "ramdisk_addr=0x800000\0" \ 279 "ramdisk_size=0x2000000\0" \ 280 "fdt_high=0xa0000000\0" \ 281 "initrd_high=0xffffffffffffffff\0" \ 282 "fdt_addr=0x64f00000\0" \ 283 "kernel_addr=0x1000000\0" \ 284 "kernel_addr_sd=0x8000\0" \ 285 "kernel_start=0x580100000\0" \ 286 "kernelheader_start=0x580800000\0" \ 287 "scriptaddr=0x80000000\0" \ 288 "scripthdraddr=0x80080000\0" \ 289 "fdtheader_addr_r=0x80100000\0" \ 290 "kernelheader_addr=0x800000\0" \ 291 "kernelheader_addr_r=0x80200000\0" \ 292 "kernel_addr_r=0x81000000\0" \ 293 "kernelheader_size=0x40000\0" \ 294 "fdt_addr_r=0x90000000\0" \ 295 "load_addr=0xa0000000\0" \ 296 "kernel_size=0x2800000\0" \ 297 "kernel_size_sd=0x14000\0" \ 298 MC_INIT_CMD \ 299 BOOTENV \ 300 "boot_scripts=ls1088ardb_boot.scr\0" \ 301 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 302 "scan_dev_for_boot_part=" \ 303 "part list ${devtype} ${devnum} devplist; " \ 304 "env exists devplist || setenv devplist 1; " \ 305 "for distro_bootpart in ${devplist}; do " \ 306 "if fstype ${devtype} " \ 307 "${devnum}:${distro_bootpart} " \ 308 "bootfstype; then " \ 309 "run scan_dev_for_boot; " \ 310 "fi; " \ 311 "done\0" \ 312 "scan_dev_for_boot=" \ 313 "echo Scanning ${devtype} " \ 314 "${devnum}:${distro_bootpart}...; " \ 315 "for prefix in ${boot_prefixes}; do " \ 316 "run scan_dev_for_scripts; " \ 317 "done;\0" \ 318 "boot_a_script=" \ 319 "load ${devtype} ${devnum}:${distro_bootpart} " \ 320 "${scriptaddr} ${prefix}${script}; " \ 321 "env exists secureboot && load ${devtype} " \ 322 "${devnum}:${distro_bootpart} " \ 323 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 324 "&& esbc_validate ${scripthdraddr};" \ 325 "source ${scriptaddr}\0" \ 326 "installer=load mmc 0:2 $load_addr " \ 327 "/flex_installer_arm64.itb; " \ 328 "env exists mcinitcmd && run mcinitcmd && " \ 329 "mmc read 0x80200000 0x6800 0x800;" \ 330 "fsl_mc apply dpl 0x80200000;" \ 331 "bootm $load_addr#ls1088ardb\0" \ 332 "qspi_bootcmd=echo Trying load from qspi..;" \ 333 "sf probe && sf read $load_addr " \ 334 "$kernel_addr $kernel_size &&" \ 335 "bootm $load_addr#$BOARD\0" \ 336 "sd_bootcmd=echo Trying load from sd card..;" \ 337 "mmcinfo; mmc read $load_addr " \ 338 "$kernel_addr_sd $kernel_size_sd ;" \ 339 "bootm $load_addr#$BOARD\0" 340 341 #undef CONFIG_BOOTCOMMAND 342 #if defined(CONFIG_QSPI_BOOT) 343 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 344 #define CONFIG_BOOTCOMMAND \ 345 "env exists mcinitcmd && run mcinitcmd && " \ 346 "sf read 0x80200000 0xd00000 0x100000;" \ 347 " fsl_mc apply dpl 0x80200000;" \ 348 "run distro_bootcmd;run qspi_bootcmd" 349 /* Try to boot an on-SD kernel first, then do normal distro boot */ 350 #elif defined(CONFIG_SD_BOOT) 351 #define CONFIG_BOOTCOMMAND \ 352 "env exists mcinitcmd && run mcinitcmd ;" \ 353 "&& env exists mcinitcmd && mmcinfo; " \ 354 "mmc read 0x88000000 0x6800 0x800; " \ 355 "&& fsl_mc apply dpl 0x88000000;" \ 356 "run distro_bootcmd;run sd_bootcmd" 357 #endif 358 359 /* MAC/PHY configuration */ 360 #ifdef CONFIG_FSL_MC_ENET 361 #define CONFIG_PHYLIB_10G 362 #define CONFIG_PHY_GIGE 363 #define CONFIG_PHYLIB 364 365 #define CONFIG_PHY_VITESSE 366 #define CONFIG_PHY_AQUANTIA 367 #define AQ_PHY_ADDR1 0x00 368 #define AQR105_IRQ_MASK 0x00000004 369 370 #define QSGMII1_PORT1_PHY_ADDR 0x0c 371 #define QSGMII1_PORT2_PHY_ADDR 0x0d 372 #define QSGMII1_PORT3_PHY_ADDR 0x0e 373 #define QSGMII1_PORT4_PHY_ADDR 0x0f 374 #define QSGMII2_PORT1_PHY_ADDR 0x1c 375 #define QSGMII2_PORT2_PHY_ADDR 0x1d 376 #define QSGMII2_PORT3_PHY_ADDR 0x1e 377 #define QSGMII2_PORT4_PHY_ADDR 0x1f 378 379 #define CONFIG_MII 380 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 381 #define CONFIG_PHY_GIGE 382 #endif 383 384 /* MMC */ 385 #ifdef CONFIG_MMC 386 #define CONFIG_FSL_ESDHC 387 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 388 #endif 389 390 #undef CONFIG_CMDLINE_EDITING 391 #include <config_distro_defaults.h> 392 393 #define BOOT_TARGET_DEVICES(func) \ 394 func(MMC, mmc, 0) \ 395 func(SCSI, scsi, 0) \ 396 func(DHCP, dhcp, na) 397 #include <config_distro_bootcmd.h> 398 399 #include <asm/fsl_secure_boot.h> 400 401 #endif /* __LS1088A_RDB_H */ 402