1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO_LATE 13 14 #if defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_ENV_IS_IN_SPI_FLASH 16 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 17 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 18 #define CONFIG_ENV_SECT_SIZE 0x40000 19 #else 20 #define CONFIG_ENV_IS_IN_FLASH 21 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 22 #define CONFIG_ENV_SECT_SIZE 0x20000 23 #define CONFIG_ENV_SIZE 0x20000 24 #endif 25 26 #if defined(CONFIG_QSPI_BOOT) 27 #define CONFIG_QIXIS_I2C_ACCESS 28 #define SYS_NO_FLASH 29 #endif 30 31 #define CONFIG_SYS_CLK_FREQ 100000000 32 #define CONFIG_DDR_CLK_FREQ 100000000 33 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 35 36 #define CONFIG_DDR_SPD 37 #ifdef CONFIG_EMU 38 #define CONFIG_SYS_FSL_DDR_EMU 39 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 40 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 41 #else 42 #define CONFIG_DDR_ECC 43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 44 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 45 #endif 46 #define SPD_EEPROM_ADDRESS 0x51 47 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 49 50 51 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 52 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 53 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 54 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 55 56 #define CONFIG_SYS_NOR0_CSPR \ 57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 58 CSPR_PORT_SIZE_16 | \ 59 CSPR_MSEL_NOR | \ 60 CSPR_V) 61 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 62 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 63 CSPR_PORT_SIZE_16 | \ 64 CSPR_MSEL_NOR | \ 65 CSPR_V) 66 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 67 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 68 FTIM0_NOR_TEADC(0x1) | \ 69 FTIM0_NOR_TEAHC(0x1)) 70 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 71 FTIM1_NOR_TRAD_NOR(0x1)) 72 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 73 FTIM2_NOR_TCH(0x0) | \ 74 FTIM2_NOR_TWP(0x1)) 75 #define CONFIG_SYS_NOR_FTIM3 0x04000000 76 #define CONFIG_SYS_IFC_CCR 0x01000000 77 78 #ifndef SYS_NO_FLASH 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 82 #define CONFIG_SYS_FLASH_QUIET_TEST 83 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 84 85 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 86 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 87 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 88 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 89 90 #define CONFIG_SYS_FLASH_EMPTY_INFO 91 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 92 #endif 93 #endif 94 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 95 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 96 97 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 98 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 99 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 100 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 101 | CSPR_V) 102 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 103 104 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 106 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 107 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 108 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 109 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 110 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 111 112 #define CONFIG_SYS_NAND_ONFI_DETECTION 113 114 /* ONFI NAND Flash mode0 Timing Params */ 115 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 116 FTIM0_NAND_TWP(0x18) | \ 117 FTIM0_NAND_TWCHT(0x07) | \ 118 FTIM0_NAND_TWH(0x0a)) 119 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 120 FTIM1_NAND_TWBE(0x39) | \ 121 FTIM1_NAND_TRR(0x0e) | \ 122 FTIM1_NAND_TRP(0x18)) 123 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 124 FTIM2_NAND_TREH(0x0a) | \ 125 FTIM2_NAND_TWHRE(0x1e)) 126 #define CONFIG_SYS_NAND_FTIM3 0x0 127 128 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 129 #define CONFIG_SYS_MAX_NAND_DEVICE 1 130 #define CONFIG_MTD_NAND_VERIFY_WRITE 131 132 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 133 134 #define CONFIG_FSL_QIXIS 135 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 136 #define QIXIS_LBMAP_SWITCH 2 137 #define QIXIS_QMAP_MASK 0xe0 138 #define QIXIS_QMAP_SHIFT 5 139 #define QIXIS_LBMAP_MASK 0x1f 140 #define QIXIS_LBMAP_SHIFT 5 141 #define QIXIS_LBMAP_DFLTBANK 0x00 142 #define QIXIS_LBMAP_ALTBANK 0x20 143 #define QIXIS_LBMAP_SD 0x00 144 #define QIXIS_LBMAP_SD_QSPI 0x00 145 #define QIXIS_LBMAP_QSPI 0x00 146 #define QIXIS_RCW_SRC_SD 0x40 147 #define QIXIS_RCW_SRC_QSPI 0x62 148 #define QIXIS_RST_CTL_RESET 0x31 149 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 150 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 151 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 152 #define QIXIS_RST_FORCE_MEM 0x01 153 154 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 155 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 156 | CSPR_PORT_SIZE_8 \ 157 | CSPR_MSEL_GPCM \ 158 | CSPR_V) 159 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 160 | CSPR_PORT_SIZE_8 \ 161 | CSPR_MSEL_GPCM \ 162 | CSPR_V) 163 164 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 165 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 166 /* QIXIS Timing parameters*/ 167 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 168 FTIM0_GPCM_TEADC(0x0e) | \ 169 FTIM0_GPCM_TEAHC(0x0e)) 170 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 171 FTIM1_GPCM_TRAD(0x3f)) 172 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 173 FTIM2_GPCM_TCH(0xf) | \ 174 FTIM2_GPCM_TWP(0x3E)) 175 #define SYS_FPGA_CS_FTIM3 0x0 176 177 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 178 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 179 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 180 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 181 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 182 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 183 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 184 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 185 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 186 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 187 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 188 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 189 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 190 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 191 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 192 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 193 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 194 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 195 #else 196 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 197 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 198 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 199 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 200 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 201 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 202 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 203 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 204 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 205 #endif 206 207 208 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 209 210 /* 211 * I2C bus multiplexer 212 */ 213 #define I2C_MUX_PCA_ADDR_PRI 0x77 214 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 215 #define I2C_RETIMER_ADDR 0x18 216 #define I2C_MUX_CH_DEFAULT 0x8 217 #define I2C_MUX_CH5 0xD 218 /* 219 * RTC configuration 220 */ 221 #define RTC 222 #define CONFIG_RTC_PCF8563 1 223 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 224 #define CONFIG_CMD_DATE 225 226 /* EEPROM */ 227 #define CONFIG_ID_EEPROM 228 #define CONFIG_SYS_I2C_EEPROM_NXID 229 #define CONFIG_SYS_EEPROM_BUS_NUM 0 230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 234 235 /* QSPI device */ 236 #if defined(CONFIG_QSPI_BOOT) 237 #define CONFIG_FSL_QSPI 238 #define CONFIG_SPI_FLASH_SPANSION 239 #define FSL_QSPI_FLASH_SIZE (1 << 26) 240 #define FSL_QSPI_FLASH_NUM 2 241 #endif 242 243 #define CONFIG_CMD_MEMINFO 244 #define CONFIG_CMD_MEMTEST 245 #define CONFIG_SYS_MEMTEST_START 0x80000000 246 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 247 248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 249 250 #define CONFIG_FSL_MEMAC 251 252 /* Initial environment variables */ 253 #if defined(CONFIG_QSPI_BOOT) 254 #undef CONFIG_EXTRA_ENV_SETTINGS 255 #define CONFIG_EXTRA_ENV_SETTINGS \ 256 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 257 "loadaddr=0x90100000\0" \ 258 "kernel_addr=0x100000\0" \ 259 "ramdisk_addr=0x800000\0" \ 260 "ramdisk_size=0x2000000\0" \ 261 "fdt_high=0xa0000000\0" \ 262 "initrd_high=0xffffffffffffffff\0" \ 263 "kernel_start=0x1000000\0" \ 264 "kernel_load=0xa0000000\0" \ 265 "kernel_size=0x2800000\0" \ 266 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 267 "sf read 0x80100000 0xE00000 0x100000;" \ 268 "fsl_mc start mc 0x80000000 0x80100000\0" \ 269 "mcmemsize=0x70000000 \0" 270 271 #endif 272 273 /* MAC/PHY configuration */ 274 #ifdef CONFIG_FSL_MC_ENET 275 #define CONFIG_PHYLIB_10G 276 #define CONFIG_PHY_GIGE 277 #define CONFIG_PHYLIB 278 279 #define CONFIG_PHY_VITESSE 280 #define CONFIG_PHY_AQUANTIA 281 #define AQ_PHY_ADDR1 0x00 282 #define AQR105_IRQ_MASK 0x00000004 283 284 #define QSGMII1_PORT1_PHY_ADDR 0x0c 285 #define QSGMII1_PORT2_PHY_ADDR 0x0d 286 #define QSGMII1_PORT3_PHY_ADDR 0x0e 287 #define QSGMII1_PORT4_PHY_ADDR 0x0f 288 #define QSGMII2_PORT1_PHY_ADDR 0x1c 289 #define QSGMII2_PORT2_PHY_ADDR 0x1d 290 #define QSGMII2_PORT3_PHY_ADDR 0x1e 291 #define QSGMII2_PORT4_PHY_ADDR 0x1f 292 293 #define CONFIG_MII 294 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 295 #define CONFIG_PHY_GIGE 296 #endif 297 298 /* MMC */ 299 #ifdef CONFIG_MMC 300 #define CONFIG_FSL_ESDHC 301 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 302 #endif 303 304 #undef CONFIG_CMDLINE_EDITING 305 #include <config_distro_defaults.h> 306 307 #define BOOT_TARGET_DEVICES(func) \ 308 func(USB, usb, 0) \ 309 func(MMC, mmc, 0) \ 310 func(SCSI, scsi, 0) \ 311 func(DHCP, dhcp, na) 312 #include <config_distro_bootcmd.h> 313 314 #include <asm/fsl_secure_boot.h> 315 316 #endif /* __LS1088A_RDB_H */ 317