1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO_LATE 13 14 #if defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 16 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 17 #define CONFIG_ENV_SECT_SIZE 0x40000 18 #elif defined(CONFIG_SD_BOOT) 19 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 20 #define CONFIG_SYS_MMC_ENV_DEV 0 21 #define CONFIG_ENV_SIZE 0x2000 22 #else 23 #define CONFIG_ENV_IS_IN_FLASH 24 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 25 #define CONFIG_ENV_SECT_SIZE 0x20000 26 #define CONFIG_ENV_SIZE 0x20000 27 #endif 28 29 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 30 #define CONFIG_QIXIS_I2C_ACCESS 31 #define SYS_NO_FLASH 32 #undef CONFIG_CMD_IMLS 33 #endif 34 35 #define CONFIG_SYS_CLK_FREQ 100000000 36 #define CONFIG_DDR_CLK_FREQ 100000000 37 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 38 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 39 40 #define CONFIG_DDR_SPD 41 #ifdef CONFIG_EMU 42 #define CONFIG_SYS_FSL_DDR_EMU 43 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 44 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 45 #else 46 #define CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 #define SPD_EEPROM_ADDRESS 0x51 51 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 54 55 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 56 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 57 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 58 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 59 60 #define CONFIG_SYS_NOR0_CSPR \ 61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 62 CSPR_PORT_SIZE_16 | \ 63 CSPR_MSEL_NOR | \ 64 CSPR_V) 65 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 67 CSPR_PORT_SIZE_16 | \ 68 CSPR_MSEL_NOR | \ 69 CSPR_V) 70 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 71 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 72 FTIM0_NOR_TEADC(0x1) | \ 73 FTIM0_NOR_TEAHC(0x1)) 74 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 75 FTIM1_NOR_TRAD_NOR(0x1)) 76 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 77 FTIM2_NOR_TCH(0x0) | \ 78 FTIM2_NOR_TWP(0x1)) 79 #define CONFIG_SYS_NOR_FTIM3 0x04000000 80 #define CONFIG_SYS_IFC_CCR 0x01000000 81 82 #ifndef SYS_NO_FLASH 83 #define CONFIG_FLASH_CFI_DRIVER 84 #define CONFIG_SYS_FLASH_CFI 85 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 86 #define CONFIG_SYS_FLASH_QUIET_TEST 87 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 88 89 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 90 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 91 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 92 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 93 94 #define CONFIG_SYS_FLASH_EMPTY_INFO 95 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 96 #endif 97 #endif 98 #define CONFIG_NAND_FSL_IFC 99 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 100 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 101 102 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 103 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 104 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 105 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 106 | CSPR_V) 107 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 108 109 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 110 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 111 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 112 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 113 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 114 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 115 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 116 117 #define CONFIG_SYS_NAND_ONFI_DETECTION 118 119 /* ONFI NAND Flash mode0 Timing Params */ 120 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 121 FTIM0_NAND_TWP(0x18) | \ 122 FTIM0_NAND_TWCHT(0x07) | \ 123 FTIM0_NAND_TWH(0x0a)) 124 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 125 FTIM1_NAND_TWBE(0x39) | \ 126 FTIM1_NAND_TRR(0x0e) | \ 127 FTIM1_NAND_TRP(0x18)) 128 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 129 FTIM2_NAND_TREH(0x0a) | \ 130 FTIM2_NAND_TWHRE(0x1e)) 131 #define CONFIG_SYS_NAND_FTIM3 0x0 132 133 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 135 #define CONFIG_MTD_NAND_VERIFY_WRITE 136 #define CONFIG_CMD_NAND 137 138 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 139 140 #define CONFIG_FSL_QIXIS 141 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 142 #define QIXIS_LBMAP_SWITCH 2 143 #define QIXIS_QMAP_MASK 0xe0 144 #define QIXIS_QMAP_SHIFT 5 145 #define QIXIS_LBMAP_MASK 0x1f 146 #define QIXIS_LBMAP_SHIFT 5 147 #define QIXIS_LBMAP_DFLTBANK 0x00 148 #define QIXIS_LBMAP_ALTBANK 0x20 149 #define QIXIS_LBMAP_SD 0x00 150 #define QIXIS_LBMAP_SD_QSPI 0x00 151 #define QIXIS_LBMAP_QSPI 0x00 152 #define QIXIS_RCW_SRC_SD 0x40 153 #define QIXIS_RCW_SRC_QSPI 0x62 154 #define QIXIS_RST_CTL_RESET 0x31 155 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 156 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 157 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 158 #define QIXIS_RST_FORCE_MEM 0x01 159 160 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 161 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 162 | CSPR_PORT_SIZE_8 \ 163 | CSPR_MSEL_GPCM \ 164 | CSPR_V) 165 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 166 | CSPR_PORT_SIZE_8 \ 167 | CSPR_MSEL_GPCM \ 168 | CSPR_V) 169 170 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 171 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 172 /* QIXIS Timing parameters*/ 173 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 174 FTIM0_GPCM_TEADC(0x0e) | \ 175 FTIM0_GPCM_TEAHC(0x0e)) 176 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 177 FTIM1_GPCM_TRAD(0x3f)) 178 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 179 FTIM2_GPCM_TCH(0xf) | \ 180 FTIM2_GPCM_TWP(0x3E)) 181 #define SYS_FPGA_CS_FTIM3 0x0 182 183 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 184 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 185 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 186 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 187 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 188 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 189 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 190 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 191 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 192 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 193 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 194 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 195 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 196 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 197 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 198 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 199 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 200 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 201 #else 202 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 203 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 204 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 205 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 206 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 207 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 208 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 209 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 210 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 211 #endif 212 213 214 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 215 216 /* 217 * I2C bus multiplexer 218 */ 219 #define I2C_MUX_PCA_ADDR_PRI 0x77 220 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 221 #define I2C_RETIMER_ADDR 0x18 222 #define I2C_MUX_CH_DEFAULT 0x8 223 #define I2C_MUX_CH5 0xD 224 /* 225 * RTC configuration 226 */ 227 #define RTC 228 #define CONFIG_RTC_PCF8563 1 229 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 230 #define CONFIG_CMD_DATE 231 232 /* EEPROM */ 233 #define CONFIG_ID_EEPROM 234 #define CONFIG_SYS_I2C_EEPROM_NXID 235 #define CONFIG_SYS_EEPROM_BUS_NUM 0 236 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 240 241 /* QSPI device */ 242 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 243 #define CONFIG_FSL_QSPI 244 #define FSL_QSPI_FLASH_SIZE (1 << 26) 245 #define FSL_QSPI_FLASH_NUM 2 246 #endif 247 248 #define CONFIG_CMD_MEMINFO 249 #define CONFIG_CMD_MEMTEST 250 #define CONFIG_SYS_MEMTEST_START 0x80000000 251 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 252 253 #ifdef CONFIG_SPL_BUILD 254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 255 #else 256 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 257 #endif 258 259 #define CONFIG_FSL_MEMAC 260 261 /* Initial environment variables */ 262 #if defined(CONFIG_QSPI_BOOT) 263 #define MC_INIT_CMD \ 264 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 265 "sf read 0x80100000 0xE00000 0x100000;" \ 266 "env exists secureboot && " \ 267 "sf read 0x80700000 0x700000 0x40000 && " \ 268 "sf read 0x80740000 0x740000 0x40000 && " \ 269 "esbc_validate 0x80700000 && " \ 270 "esbc_validate 0x80740000 ;" \ 271 "fsl_mc start mc 0x80000000 0x80100000\0" \ 272 "mcmemsize=0x70000000\0" 273 #elif defined(CONFIG_SD_BOOT) 274 #define MC_INIT_CMD \ 275 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 276 "mmc read 0x80100000 0x7000 0x800;" \ 277 "env exists secureboot && " \ 278 "mmc read 0x80700000 0x3800 0x10 && " \ 279 "mmc read 0x80740000 0x3A00 0x10 && " \ 280 "esbc_validate 0x80700000 && " \ 281 "esbc_validate 0x80740000 ;" \ 282 "fsl_mc start mc 0x80000000 0x80100000\0" \ 283 "mcmemsize=0x70000000\0" 284 #endif 285 286 #undef CONFIG_EXTRA_ENV_SETTINGS 287 #define CONFIG_EXTRA_ENV_SETTINGS \ 288 "BOARD=ls1088ardb\0" \ 289 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 290 "ramdisk_addr=0x800000\0" \ 291 "ramdisk_size=0x2000000\0" \ 292 "fdt_high=0xa0000000\0" \ 293 "initrd_high=0xffffffffffffffff\0" \ 294 "fdt_addr=0x64f00000\0" \ 295 "kernel_addr=0x1000000\0" \ 296 "kernel_addr_sd=0x8000\0" \ 297 "kernelhdr_addr_sd=0x4000\0" \ 298 "kernel_start=0x580100000\0" \ 299 "kernelheader_start=0x580800000\0" \ 300 "scriptaddr=0x80000000\0" \ 301 "scripthdraddr=0x80080000\0" \ 302 "fdtheader_addr_r=0x80100000\0" \ 303 "kernelheader_addr=0x800000\0" \ 304 "kernelheader_addr_r=0x80200000\0" \ 305 "kernel_addr_r=0x81000000\0" \ 306 "kernelheader_size=0x40000\0" \ 307 "fdt_addr_r=0x90000000\0" \ 308 "load_addr=0xa0000000\0" \ 309 "kernel_size=0x2800000\0" \ 310 "kernel_size_sd=0x14000\0" \ 311 "kernelhdr_size_sd=0x10\0" \ 312 MC_INIT_CMD \ 313 BOOTENV \ 314 "boot_scripts=ls1088ardb_boot.scr\0" \ 315 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 316 "scan_dev_for_boot_part=" \ 317 "part list ${devtype} ${devnum} devplist; " \ 318 "env exists devplist || setenv devplist 1; " \ 319 "for distro_bootpart in ${devplist}; do " \ 320 "if fstype ${devtype} " \ 321 "${devnum}:${distro_bootpart} " \ 322 "bootfstype; then " \ 323 "run scan_dev_for_boot; " \ 324 "fi; " \ 325 "done\0" \ 326 "scan_dev_for_boot=" \ 327 "echo Scanning ${devtype} " \ 328 "${devnum}:${distro_bootpart}...; " \ 329 "for prefix in ${boot_prefixes}; do " \ 330 "run scan_dev_for_scripts; " \ 331 "done;\0" \ 332 "boot_a_script=" \ 333 "load ${devtype} ${devnum}:${distro_bootpart} " \ 334 "${scriptaddr} ${prefix}${script}; " \ 335 "env exists secureboot && load ${devtype} " \ 336 "${devnum}:${distro_bootpart} " \ 337 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 338 "&& esbc_validate ${scripthdraddr};" \ 339 "source ${scriptaddr}\0" \ 340 "installer=load mmc 0:2 $load_addr " \ 341 "/flex_installer_arm64.itb; " \ 342 "env exists mcinitcmd && run mcinitcmd && " \ 343 "mmc read 0x80200000 0x6800 0x800;" \ 344 "fsl_mc apply dpl 0x80200000;" \ 345 "bootm $load_addr#ls1088ardb\0" \ 346 "qspi_bootcmd=echo Trying load from qspi..;" \ 347 "sf probe && sf read $load_addr " \ 348 "$kernel_addr $kernel_size ; env exists secureboot " \ 349 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 350 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 351 "bootm $load_addr#$BOARD\0" \ 352 "sd_bootcmd=echo Trying load from sd card..;" \ 353 "mmcinfo; mmc read $load_addr " \ 354 "$kernel_addr_sd $kernel_size_sd ;" \ 355 "env exists secureboot && mmc read $kernelheader_addr_r "\ 356 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 357 " && esbc_validate ${kernelheader_addr_r};" \ 358 "bootm $load_addr#$BOARD\0" 359 360 #undef CONFIG_BOOTCOMMAND 361 #if defined(CONFIG_QSPI_BOOT) 362 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 363 #define CONFIG_BOOTCOMMAND \ 364 "sf read 0x80200000 0xd00000 0x100000;" \ 365 "env exists mcinitcmd && env exists secureboot " \ 366 " && sf read 0x80780000 0x780000 0x100000 " \ 367 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 368 "&& fsl_mc apply dpl 0x80200000;" \ 369 "run distro_bootcmd;run qspi_bootcmd;" \ 370 "env exists secureboot && esbc_halt;" 371 372 /* Try to boot an on-SD kernel first, then do normal distro boot */ 373 #elif defined(CONFIG_SD_BOOT) 374 #define CONFIG_BOOTCOMMAND \ 375 "env exists mcinitcmd && mmcinfo; " \ 376 "mmc read 0x80200000 0x6800 0x800; " \ 377 "env exists mcinitcmd && env exists secureboot " \ 378 " && mmc read 0x80780000 0x3800 0x10 " \ 379 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 380 "&& fsl_mc apply dpl 0x80200000;" \ 381 "run distro_bootcmd;run sd_bootcmd;" \ 382 "env exists secureboot && esbc_halt;" 383 #endif 384 385 /* MAC/PHY configuration */ 386 #ifdef CONFIG_FSL_MC_ENET 387 #define CONFIG_PHYLIB_10G 388 #define CONFIG_PHY_GIGE 389 #define CONFIG_PHYLIB 390 391 #define CONFIG_PHY_VITESSE 392 #define CONFIG_PHY_AQUANTIA 393 #define AQ_PHY_ADDR1 0x00 394 #define AQR105_IRQ_MASK 0x00000004 395 396 #define QSGMII1_PORT1_PHY_ADDR 0x0c 397 #define QSGMII1_PORT2_PHY_ADDR 0x0d 398 #define QSGMII1_PORT3_PHY_ADDR 0x0e 399 #define QSGMII1_PORT4_PHY_ADDR 0x0f 400 #define QSGMII2_PORT1_PHY_ADDR 0x1c 401 #define QSGMII2_PORT2_PHY_ADDR 0x1d 402 #define QSGMII2_PORT3_PHY_ADDR 0x1e 403 #define QSGMII2_PORT4_PHY_ADDR 0x1f 404 405 #define CONFIG_MII 406 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 407 #define CONFIG_PHY_GIGE 408 #endif 409 410 /* MMC */ 411 #ifdef CONFIG_MMC 412 #define CONFIG_FSL_ESDHC 413 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 414 #endif 415 416 #undef CONFIG_CMDLINE_EDITING 417 #include <config_distro_defaults.h> 418 419 #define BOOT_TARGET_DEVICES(func) \ 420 func(MMC, mmc, 0) \ 421 func(SCSI, scsi, 0) \ 422 func(DHCP, dhcp, na) 423 #include <config_distro_bootcmd.h> 424 425 #include <asm/fsl_secure_boot.h> 426 427 #endif /* __LS1088A_RDB_H */ 428