1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __LS1088A_RDB_H 7 #define __LS1088A_RDB_H 8 9 #include "ls1088a_common.h" 10 11 #if defined(CONFIG_QSPI_BOOT) 12 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 13 #define CONFIG_ENV_SECT_SIZE 0x40000 14 #elif defined(CONFIG_SD_BOOT) 15 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 16 #define CONFIG_SYS_MMC_ENV_DEV 0 17 #define CONFIG_ENV_SIZE 0x2000 18 #else 19 #define CONFIG_ENV_IS_IN_FLASH 20 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 21 #define CONFIG_ENV_SECT_SIZE 0x20000 22 #define CONFIG_ENV_SIZE 0x20000 23 #endif 24 25 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 26 #ifndef CONFIG_SPL_BUILD 27 #define CONFIG_QIXIS_I2C_ACCESS 28 #endif 29 #define SYS_NO_FLASH 30 #undef CONFIG_CMD_IMLS 31 #endif 32 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000 35 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 36 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 37 38 #define CONFIG_DDR_SPD 39 #ifdef CONFIG_EMU 40 #define CONFIG_SYS_FSL_DDR_EMU 41 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 42 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 43 #else 44 #define CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 #define SPD_EEPROM_ADDRESS 0x51 49 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 52 53 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 54 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 55 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 56 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 57 58 #define CONFIG_SYS_NOR0_CSPR \ 59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 60 CSPR_PORT_SIZE_16 | \ 61 CSPR_MSEL_NOR | \ 62 CSPR_V) 63 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 65 CSPR_PORT_SIZE_16 | \ 66 CSPR_MSEL_NOR | \ 67 CSPR_V) 68 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 69 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 70 FTIM0_NOR_TEADC(0x1) | \ 71 FTIM0_NOR_TEAHC(0x1)) 72 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 73 FTIM1_NOR_TRAD_NOR(0x1)) 74 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 75 FTIM2_NOR_TCH(0x0) | \ 76 FTIM2_NOR_TWP(0x1)) 77 #define CONFIG_SYS_NOR_FTIM3 0x04000000 78 #define CONFIG_SYS_IFC_CCR 0x01000000 79 80 #ifndef SYS_NO_FLASH 81 #define CONFIG_FLASH_CFI_DRIVER 82 #define CONFIG_SYS_FLASH_CFI 83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 84 #define CONFIG_SYS_FLASH_QUIET_TEST 85 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 86 87 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 91 92 #define CONFIG_SYS_FLASH_EMPTY_INFO 93 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 94 #endif 95 #endif 96 97 #ifndef SPL_NO_IFC 98 #define CONFIG_NAND_FSL_IFC 99 #endif 100 101 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 102 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 103 104 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 105 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 106 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 107 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 108 | CSPR_V) 109 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 110 111 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 112 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 113 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 114 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 115 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 116 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 117 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 118 119 #define CONFIG_SYS_NAND_ONFI_DETECTION 120 121 /* ONFI NAND Flash mode0 Timing Params */ 122 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 123 FTIM0_NAND_TWP(0x18) | \ 124 FTIM0_NAND_TWCHT(0x07) | \ 125 FTIM0_NAND_TWH(0x0a)) 126 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 127 FTIM1_NAND_TWBE(0x39) | \ 128 FTIM1_NAND_TRR(0x0e) | \ 129 FTIM1_NAND_TRP(0x18)) 130 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 131 FTIM2_NAND_TREH(0x0a) | \ 132 FTIM2_NAND_TWHRE(0x1e)) 133 #define CONFIG_SYS_NAND_FTIM3 0x0 134 135 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 137 #define CONFIG_MTD_NAND_VERIFY_WRITE 138 #define CONFIG_CMD_NAND 139 140 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 141 142 #ifndef SPL_NO_QIXIS 143 #define CONFIG_FSL_QIXIS 144 #endif 145 146 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 147 #define QIXIS_BRDCFG4_OFFSET 0x54 148 #define QIXIS_LBMAP_SWITCH 2 149 #define QIXIS_QMAP_MASK 0xe0 150 #define QIXIS_QMAP_SHIFT 5 151 #define QIXIS_LBMAP_MASK 0x1f 152 #define QIXIS_LBMAP_SHIFT 5 153 #define QIXIS_LBMAP_DFLTBANK 0x00 154 #define QIXIS_LBMAP_ALTBANK 0x20 155 #define QIXIS_LBMAP_SD 0x00 156 #define QIXIS_LBMAP_EMMC 0x00 157 #define QIXIS_LBMAP_SD_QSPI 0x00 158 #define QIXIS_LBMAP_QSPI 0x00 159 #define QIXIS_RCW_SRC_SD 0x40 160 #define QIXIS_RCW_SRC_EMMC 0x41 161 #define QIXIS_RCW_SRC_QSPI 0x62 162 #define QIXIS_RST_CTL_RESET 0x31 163 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 164 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 165 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 166 #define QIXIS_RST_FORCE_MEM 0x01 167 168 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 169 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 170 | CSPR_PORT_SIZE_8 \ 171 | CSPR_MSEL_GPCM \ 172 | CSPR_V) 173 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 174 | CSPR_PORT_SIZE_8 \ 175 | CSPR_MSEL_GPCM \ 176 | CSPR_V) 177 178 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 179 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 180 /* QIXIS Timing parameters*/ 181 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 182 FTIM0_GPCM_TEADC(0x0e) | \ 183 FTIM0_GPCM_TEAHC(0x0e)) 184 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 185 FTIM1_GPCM_TRAD(0x3f)) 186 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 187 FTIM2_GPCM_TCH(0xf) | \ 188 FTIM2_GPCM_TWP(0x3E)) 189 #define SYS_FPGA_CS_FTIM3 0x0 190 191 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 192 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 193 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 194 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 195 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 196 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 197 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 198 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 199 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 200 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 201 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 202 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 203 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 204 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 205 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 206 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 207 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 208 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 209 #else 210 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 211 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 212 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 213 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 214 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 215 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 216 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 217 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 218 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 219 #endif 220 221 222 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 223 224 #define I2C_MUX_CH_VOL_MONITOR 0xA 225 /* Voltage monitor on channel 2*/ 226 #define I2C_VOL_MONITOR_ADDR 0x63 227 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 228 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 229 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 230 #define I2C_SVDD_MONITOR_ADDR 0x4F 231 232 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" 233 #define CONFIG_VID 234 235 /* The lowest and highest voltage allowed for LS1088ARDB */ 236 #define VDD_MV_MIN 819 237 #define VDD_MV_MAX 1212 238 239 #define CONFIG_VOL_MONITOR_LTC3882_SET 240 #define CONFIG_VOL_MONITOR_LTC3882_READ 241 242 /* PM Bus commands code for LTC3882*/ 243 #define PMBUS_CMD_PAGE 0x0 244 #define PMBUS_CMD_READ_VOUT 0x8B 245 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 246 #define PMBUS_CMD_VOUT_COMMAND 0x21 247 248 #define PWM_CHANNEL0 0x0 249 250 /* 251 * I2C bus multiplexer 252 */ 253 #define I2C_MUX_PCA_ADDR_PRI 0x77 254 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 255 #define I2C_RETIMER_ADDR 0x18 256 #define I2C_MUX_CH_DEFAULT 0x8 257 #define I2C_MUX_CH5 0xD 258 259 #ifndef SPL_NO_RTC 260 /* 261 * RTC configuration 262 */ 263 #define RTC 264 #define CONFIG_RTC_PCF8563 1 265 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 266 #define CONFIG_CMD_DATE 267 #endif 268 269 /* EEPROM */ 270 #define CONFIG_ID_EEPROM 271 #define CONFIG_SYS_I2C_EEPROM_NXID 272 #define CONFIG_SYS_EEPROM_BUS_NUM 0 273 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 274 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 275 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 276 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 277 278 #ifndef SPL_NO_QSPI 279 /* QSPI device */ 280 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 281 #define CONFIG_FSL_QSPI 282 #define FSL_QSPI_FLASH_SIZE (1 << 26) 283 #define FSL_QSPI_FLASH_NUM 2 284 #endif 285 #endif 286 287 #define CONFIG_CMD_MEMINFO 288 #define CONFIG_SYS_MEMTEST_START 0x80000000 289 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 290 291 #ifdef CONFIG_SPL_BUILD 292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 293 #else 294 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 295 #endif 296 297 #define CONFIG_FSL_MEMAC 298 299 #ifndef SPL_NO_ENV 300 /* Initial environment variables */ 301 #if defined(CONFIG_QSPI_BOOT) 302 #define MC_INIT_CMD \ 303 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 304 "sf read 0x80100000 0xE00000 0x100000;" \ 305 "env exists secureboot && " \ 306 "sf read 0x80700000 0x700000 0x40000 && " \ 307 "sf read 0x80740000 0x740000 0x40000 && " \ 308 "esbc_validate 0x80700000 && " \ 309 "esbc_validate 0x80740000 ;" \ 310 "fsl_mc start mc 0x80000000 0x80100000\0" \ 311 "mcmemsize=0x70000000\0" 312 #elif defined(CONFIG_SD_BOOT) 313 #define MC_INIT_CMD \ 314 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 315 "mmc read 0x80100000 0x7000 0x800;" \ 316 "env exists secureboot && " \ 317 "mmc read 0x80700000 0x3800 0x10 && " \ 318 "mmc read 0x80740000 0x3A00 0x10 && " \ 319 "esbc_validate 0x80700000 && " \ 320 "esbc_validate 0x80740000 ;" \ 321 "fsl_mc start mc 0x80000000 0x80100000\0" \ 322 "mcmemsize=0x70000000\0" 323 #endif 324 325 #undef CONFIG_EXTRA_ENV_SETTINGS 326 #define CONFIG_EXTRA_ENV_SETTINGS \ 327 "BOARD=ls1088ardb\0" \ 328 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 329 "ramdisk_addr=0x800000\0" \ 330 "ramdisk_size=0x2000000\0" \ 331 "fdt_high=0xa0000000\0" \ 332 "initrd_high=0xffffffffffffffff\0" \ 333 "fdt_addr=0x64f00000\0" \ 334 "kernel_addr=0x1000000\0" \ 335 "kernel_addr_sd=0x8000\0" \ 336 "kernelhdr_addr_sd=0x4000\0" \ 337 "kernel_start=0x580100000\0" \ 338 "kernelheader_start=0x580800000\0" \ 339 "scriptaddr=0x80000000\0" \ 340 "scripthdraddr=0x80080000\0" \ 341 "fdtheader_addr_r=0x80100000\0" \ 342 "kernelheader_addr=0x800000\0" \ 343 "kernelheader_addr_r=0x80200000\0" \ 344 "kernel_addr_r=0x81000000\0" \ 345 "kernelheader_size=0x40000\0" \ 346 "fdt_addr_r=0x90000000\0" \ 347 "load_addr=0xa0000000\0" \ 348 "kernel_size=0x2800000\0" \ 349 "kernel_size_sd=0x14000\0" \ 350 "kernelhdr_size_sd=0x10\0" \ 351 MC_INIT_CMD \ 352 BOOTENV \ 353 "boot_scripts=ls1088ardb_boot.scr\0" \ 354 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 355 "scan_dev_for_boot_part=" \ 356 "part list ${devtype} ${devnum} devplist; " \ 357 "env exists devplist || setenv devplist 1; " \ 358 "for distro_bootpart in ${devplist}; do " \ 359 "if fstype ${devtype} " \ 360 "${devnum}:${distro_bootpart} " \ 361 "bootfstype; then " \ 362 "run scan_dev_for_boot; " \ 363 "fi; " \ 364 "done\0" \ 365 "scan_dev_for_boot=" \ 366 "echo Scanning ${devtype} " \ 367 "${devnum}:${distro_bootpart}...; " \ 368 "for prefix in ${boot_prefixes}; do " \ 369 "run scan_dev_for_scripts; " \ 370 "done;\0" \ 371 "boot_a_script=" \ 372 "load ${devtype} ${devnum}:${distro_bootpart} " \ 373 "${scriptaddr} ${prefix}${script}; " \ 374 "env exists secureboot && load ${devtype} " \ 375 "${devnum}:${distro_bootpart} " \ 376 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 377 "&& esbc_validate ${scripthdraddr};" \ 378 "source ${scriptaddr}\0" \ 379 "installer=load mmc 0:2 $load_addr " \ 380 "/flex_installer_arm64.itb; " \ 381 "env exists mcinitcmd && run mcinitcmd && " \ 382 "mmc read 0x80001000 0x6800 0x800;" \ 383 "fsl_mc lazyapply dpl 0x80001000;" \ 384 "bootm $load_addr#ls1088ardb\0" \ 385 "qspi_bootcmd=echo Trying load from qspi..;" \ 386 "sf probe && sf read $load_addr " \ 387 "$kernel_addr $kernel_size ; env exists secureboot " \ 388 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 389 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 390 "bootm $load_addr#$BOARD\0" \ 391 "sd_bootcmd=echo Trying load from sd card..;" \ 392 "mmcinfo; mmc read $load_addr " \ 393 "$kernel_addr_sd $kernel_size_sd ;" \ 394 "env exists secureboot && mmc read $kernelheader_addr_r "\ 395 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 396 " && esbc_validate ${kernelheader_addr_r};" \ 397 "bootm $load_addr#$BOARD\0" 398 399 #undef CONFIG_BOOTCOMMAND 400 #if defined(CONFIG_QSPI_BOOT) 401 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 402 #define CONFIG_BOOTCOMMAND \ 403 "sf read 0x80001000 0xd00000 0x100000;" \ 404 "env exists mcinitcmd && env exists secureboot " \ 405 " && sf read 0x80780000 0x780000 0x100000 " \ 406 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 407 "&& fsl_mc lazyapply dpl 0x80001000;" \ 408 "run distro_bootcmd;run qspi_bootcmd;" \ 409 "env exists secureboot && esbc_halt;" 410 411 /* Try to boot an on-SD kernel first, then do normal distro boot */ 412 #elif defined(CONFIG_SD_BOOT) 413 #define CONFIG_BOOTCOMMAND \ 414 "env exists mcinitcmd && mmcinfo; " \ 415 "mmc read 0x80001000 0x6800 0x800; " \ 416 "env exists mcinitcmd && env exists secureboot " \ 417 " && mmc read 0x80780000 0x3C00 0x10 " \ 418 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 419 "&& fsl_mc lazyapply dpl 0x80001000;" \ 420 "run distro_bootcmd;run sd_bootcmd;" \ 421 "env exists secureboot && esbc_halt;" 422 #endif 423 424 /* MAC/PHY configuration */ 425 #ifdef CONFIG_FSL_MC_ENET 426 #define CONFIG_PHYLIB_10G 427 #define CONFIG_PHY_GIGE 428 #define CONFIG_PHYLIB 429 430 #define CONFIG_PHY_VITESSE 431 #define CONFIG_PHY_AQUANTIA 432 #define AQ_PHY_ADDR1 0x00 433 #define AQR105_IRQ_MASK 0x00000004 434 435 #define QSGMII1_PORT1_PHY_ADDR 0x0c 436 #define QSGMII1_PORT2_PHY_ADDR 0x0d 437 #define QSGMII1_PORT3_PHY_ADDR 0x0e 438 #define QSGMII1_PORT4_PHY_ADDR 0x0f 439 #define QSGMII2_PORT1_PHY_ADDR 0x1c 440 #define QSGMII2_PORT2_PHY_ADDR 0x1d 441 #define QSGMII2_PORT3_PHY_ADDR 0x1e 442 #define QSGMII2_PORT4_PHY_ADDR 0x1f 443 444 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 445 #define CONFIG_PHY_GIGE 446 #endif 447 #endif 448 449 /* MMC */ 450 #ifdef CONFIG_MMC 451 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 452 #endif 453 454 #ifndef SPL_NO_ENV 455 456 #define BOOT_TARGET_DEVICES(func) \ 457 func(MMC, mmc, 0) \ 458 func(SCSI, scsi, 0) \ 459 func(DHCP, dhcp, na) 460 #include <config_distro_bootcmd.h> 461 #endif 462 463 #include <asm/fsl_secure_boot.h> 464 465 #endif /* __LS1088A_RDB_H */ 466