1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __LS1088A_RDB_H 7 #define __LS1088A_RDB_H 8 9 #include "ls1088a_common.h" 10 11 #ifdef CONFIG_TFABOOT 12 #define CONFIG_SYS_MMC_ENV_DEV 0 13 14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 15 #define CONFIG_ENV_OFFSET 0x500000 16 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 17 CONFIG_ENV_OFFSET) 18 #define CONFIG_ENV_SECT_SIZE 0x40000 19 #else 20 #if defined(CONFIG_QSPI_BOOT) 21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 22 #define CONFIG_ENV_SECT_SIZE 0x40000 23 #elif defined(CONFIG_SD_BOOT) 24 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 25 #define CONFIG_SYS_MMC_ENV_DEV 0 26 #define CONFIG_ENV_SIZE 0x2000 27 #else 28 #define CONFIG_ENV_IS_IN_FLASH 29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 30 #define CONFIG_ENV_SECT_SIZE 0x20000 31 #define CONFIG_ENV_SIZE 0x20000 32 #endif 33 #endif /* CONFIG_TFABOOT */ 34 35 #if defined(CONFIG_TFABOOT) || \ 36 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 37 #ifndef CONFIG_SPL_BUILD 38 #define CONFIG_QIXIS_I2C_ACCESS 39 #endif 40 #define SYS_NO_FLASH 41 #undef CONFIG_CMD_IMLS 42 #endif 43 44 #define CONFIG_SYS_CLK_FREQ 100000000 45 #define CONFIG_DDR_CLK_FREQ 100000000 46 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 47 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 48 49 #define CONFIG_DDR_SPD 50 #ifdef CONFIG_EMU 51 #define CONFIG_SYS_FSL_DDR_EMU 52 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 53 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 54 #else 55 #define CONFIG_DDR_ECC 56 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 58 #endif 59 #define SPD_EEPROM_ADDRESS 0x51 60 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 61 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 62 63 64 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 67 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 68 69 #define CONFIG_SYS_NOR0_CSPR \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 71 CSPR_PORT_SIZE_16 | \ 72 CSPR_MSEL_NOR | \ 73 CSPR_V) 74 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 76 CSPR_PORT_SIZE_16 | \ 77 CSPR_MSEL_NOR | \ 78 CSPR_V) 79 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 80 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 81 FTIM0_NOR_TEADC(0x1) | \ 82 FTIM0_NOR_TEAHC(0x1)) 83 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 84 FTIM1_NOR_TRAD_NOR(0x1)) 85 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 86 FTIM2_NOR_TCH(0x0) | \ 87 FTIM2_NOR_TWP(0x1)) 88 #define CONFIG_SYS_NOR_FTIM3 0x04000000 89 #define CONFIG_SYS_IFC_CCR 0x01000000 90 91 #ifndef SYS_NO_FLASH 92 #define CONFIG_SYS_FLASH_QUIET_TEST 93 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 94 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 96 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 97 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 98 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 99 100 #define CONFIG_SYS_FLASH_EMPTY_INFO 101 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 102 #endif 103 #endif 104 105 #ifndef SPL_NO_IFC 106 #define CONFIG_NAND_FSL_IFC 107 #endif 108 109 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 110 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 111 112 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 113 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 114 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 115 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 116 | CSPR_V) 117 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 118 119 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 120 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 121 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 122 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 123 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 124 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 125 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 126 127 #define CONFIG_SYS_NAND_ONFI_DETECTION 128 129 /* ONFI NAND Flash mode0 Timing Params */ 130 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 131 FTIM0_NAND_TWP(0x18) | \ 132 FTIM0_NAND_TWCHT(0x07) | \ 133 FTIM0_NAND_TWH(0x0a)) 134 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 135 FTIM1_NAND_TWBE(0x39) | \ 136 FTIM1_NAND_TRR(0x0e) | \ 137 FTIM1_NAND_TRP(0x18)) 138 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 139 FTIM2_NAND_TREH(0x0a) | \ 140 FTIM2_NAND_TWHRE(0x1e)) 141 #define CONFIG_SYS_NAND_FTIM3 0x0 142 143 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 145 #define CONFIG_MTD_NAND_VERIFY_WRITE 146 #define CONFIG_CMD_NAND 147 148 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 149 150 #ifndef SPL_NO_QIXIS 151 #define CONFIG_FSL_QIXIS 152 #endif 153 154 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 155 #define QIXIS_BRDCFG4_OFFSET 0x54 156 #define QIXIS_LBMAP_SWITCH 2 157 #define QIXIS_QMAP_MASK 0xe0 158 #define QIXIS_QMAP_SHIFT 5 159 #define QIXIS_LBMAP_MASK 0x1f 160 #define QIXIS_LBMAP_SHIFT 5 161 #define QIXIS_LBMAP_DFLTBANK 0x00 162 #define QIXIS_LBMAP_ALTBANK 0x20 163 #define QIXIS_LBMAP_SD 0x00 164 #define QIXIS_LBMAP_EMMC 0x00 165 #define QIXIS_LBMAP_SD_QSPI 0x00 166 #define QIXIS_LBMAP_QSPI 0x00 167 #define QIXIS_RCW_SRC_SD 0x40 168 #define QIXIS_RCW_SRC_EMMC 0x41 169 #define QIXIS_RCW_SRC_QSPI 0x62 170 #define QIXIS_RST_CTL_RESET 0x31 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 174 #define QIXIS_RST_FORCE_MEM 0x01 175 176 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 177 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 178 | CSPR_PORT_SIZE_8 \ 179 | CSPR_MSEL_GPCM \ 180 | CSPR_V) 181 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 182 | CSPR_PORT_SIZE_8 \ 183 | CSPR_MSEL_GPCM \ 184 | CSPR_V) 185 186 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 187 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 188 /* QIXIS Timing parameters*/ 189 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 190 FTIM0_GPCM_TEADC(0x0e) | \ 191 FTIM0_GPCM_TEAHC(0x0e)) 192 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 193 FTIM1_GPCM_TRAD(0x3f)) 194 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 195 FTIM2_GPCM_TCH(0xf) | \ 196 FTIM2_GPCM_TWP(0x3E)) 197 #define SYS_FPGA_CS_FTIM3 0x0 198 199 #if defined(CONFIG_TFABOOT) || \ 200 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 201 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 202 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 203 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 204 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 205 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 206 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 207 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 208 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 209 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 210 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 211 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 212 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 213 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 214 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 215 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 216 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 217 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 218 #else 219 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 220 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 221 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 222 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 223 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 224 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 225 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 226 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 228 #endif 229 230 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 231 232 #define I2C_MUX_CH_VOL_MONITOR 0xA 233 /* Voltage monitor on channel 2*/ 234 #define I2C_VOL_MONITOR_ADDR 0x63 235 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 236 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 237 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 238 #define I2C_SVDD_MONITOR_ADDR 0x4F 239 240 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" 241 #define CONFIG_VID 242 243 /* The lowest and highest voltage allowed for LS1088ARDB */ 244 #define VDD_MV_MIN 819 245 #define VDD_MV_MAX 1212 246 247 #define CONFIG_VOL_MONITOR_LTC3882_SET 248 #define CONFIG_VOL_MONITOR_LTC3882_READ 249 250 /* PM Bus commands code for LTC3882*/ 251 #define PMBUS_CMD_PAGE 0x0 252 #define PMBUS_CMD_READ_VOUT 0x8B 253 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 254 #define PMBUS_CMD_VOUT_COMMAND 0x21 255 256 #define PWM_CHANNEL0 0x0 257 258 /* 259 * I2C bus multiplexer 260 */ 261 #define I2C_MUX_PCA_ADDR_PRI 0x77 262 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 263 #define I2C_RETIMER_ADDR 0x18 264 #define I2C_MUX_CH_DEFAULT 0x8 265 #define I2C_MUX_CH5 0xD 266 267 #ifndef SPL_NO_RTC 268 /* 269 * RTC configuration 270 */ 271 #define RTC 272 #define CONFIG_RTC_PCF8563 1 273 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 274 #define CONFIG_CMD_DATE 275 #endif 276 277 /* EEPROM */ 278 #define CONFIG_ID_EEPROM 279 #define CONFIG_SYS_I2C_EEPROM_NXID 280 #define CONFIG_SYS_EEPROM_BUS_NUM 0 281 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 282 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 284 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 285 286 #ifndef SPL_NO_QSPI 287 /* QSPI device */ 288 #if defined(CONFIG_TFABOOT) || \ 289 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 290 #define FSL_QSPI_FLASH_SIZE (1 << 26) 291 #define FSL_QSPI_FLASH_NUM 2 292 #endif 293 #endif 294 295 #define CONFIG_CMD_MEMINFO 296 #define CONFIG_SYS_MEMTEST_START 0x80000000 297 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 298 299 #ifdef CONFIG_SPL_BUILD 300 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 301 #else 302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 303 #endif 304 305 #define CONFIG_FSL_MEMAC 306 307 #ifndef SPL_NO_ENV 308 /* Initial environment variables */ 309 #ifdef CONFIG_TFABOOT 310 #define QSPI_MC_INIT_CMD \ 311 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 312 "sf read 0x80100000 0xE00000 0x100000;" \ 313 "env exists secureboot && " \ 314 "sf read 0x80700000 0x700000 0x40000 && " \ 315 "sf read 0x80740000 0x740000 0x40000 && " \ 316 "esbc_validate 0x80700000 && " \ 317 "esbc_validate 0x80740000 ;" \ 318 "fsl_mc start mc 0x80000000 0x80100000\0" 319 #define SD_MC_INIT_CMD \ 320 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 321 "mmc read 0x80100000 0x7000 0x800;" \ 322 "env exists secureboot && " \ 323 "mmc read 0x80700000 0x3800 0x10 && " \ 324 "mmc read 0x80740000 0x3A00 0x10 && " \ 325 "esbc_validate 0x80700000 && " \ 326 "esbc_validate 0x80740000 ;" \ 327 "fsl_mc start mc 0x80000000 0x80100000\0" 328 #else 329 #if defined(CONFIG_QSPI_BOOT) 330 #define MC_INIT_CMD \ 331 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 332 "sf read 0x80100000 0xE00000 0x100000;" \ 333 "env exists secureboot && " \ 334 "sf read 0x80700000 0x700000 0x40000 && " \ 335 "sf read 0x80740000 0x740000 0x40000 && " \ 336 "esbc_validate 0x80700000 && " \ 337 "esbc_validate 0x80740000 ;" \ 338 "fsl_mc start mc 0x80000000 0x80100000\0" \ 339 "mcmemsize=0x70000000\0" 340 #elif defined(CONFIG_SD_BOOT) 341 #define MC_INIT_CMD \ 342 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 343 "mmc read 0x80100000 0x7000 0x800;" \ 344 "env exists secureboot && " \ 345 "mmc read 0x80700000 0x3800 0x10 && " \ 346 "mmc read 0x80740000 0x3A00 0x10 && " \ 347 "esbc_validate 0x80700000 && " \ 348 "esbc_validate 0x80740000 ;" \ 349 "fsl_mc start mc 0x80000000 0x80100000\0" \ 350 "mcmemsize=0x70000000\0" 351 #endif 352 #endif /* CONFIG_TFABOOT */ 353 354 #undef CONFIG_EXTRA_ENV_SETTINGS 355 #ifdef CONFIG_TFABOOT 356 #define CONFIG_EXTRA_ENV_SETTINGS \ 357 "BOARD=ls1088ardb\0" \ 358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 359 "ramdisk_addr=0x800000\0" \ 360 "ramdisk_size=0x2000000\0" \ 361 "fdt_high=0xa0000000\0" \ 362 "initrd_high=0xffffffffffffffff\0" \ 363 "fdt_addr=0x64f00000\0" \ 364 "kernel_addr=0x1000000\0" \ 365 "kernel_addr_sd=0x8000\0" \ 366 "kernelhdr_addr_sd=0x4000\0" \ 367 "kernel_start=0x580100000\0" \ 368 "kernelheader_start=0x580800000\0" \ 369 "scriptaddr=0x80000000\0" \ 370 "scripthdraddr=0x80080000\0" \ 371 "fdtheader_addr_r=0x80100000\0" \ 372 "kernelheader_addr=0x800000\0" \ 373 "kernelheader_addr_r=0x80200000\0" \ 374 "kernel_addr_r=0x81000000\0" \ 375 "kernelheader_size=0x40000\0" \ 376 "fdt_addr_r=0x90000000\0" \ 377 "load_addr=0xa0000000\0" \ 378 "kernel_size=0x2800000\0" \ 379 "kernel_size_sd=0x14000\0" \ 380 "kernelhdr_size_sd=0x10\0" \ 381 QSPI_MC_INIT_CMD \ 382 "mcmemsize=0x70000000\0" \ 383 BOOTENV \ 384 "boot_scripts=ls1088ardb_boot.scr\0" \ 385 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 386 "scan_dev_for_boot_part=" \ 387 "part list ${devtype} ${devnum} devplist; " \ 388 "env exists devplist || setenv devplist 1; " \ 389 "for distro_bootpart in ${devplist}; do " \ 390 "if fstype ${devtype} " \ 391 "${devnum}:${distro_bootpart} " \ 392 "bootfstype; then " \ 393 "run scan_dev_for_boot; " \ 394 "fi; " \ 395 "done\0" \ 396 "boot_a_script=" \ 397 "load ${devtype} ${devnum}:${distro_bootpart} " \ 398 "${scriptaddr} ${prefix}${script}; " \ 399 "env exists secureboot && load ${devtype} " \ 400 "${devnum}:${distro_bootpart} " \ 401 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 402 "&& esbc_validate ${scripthdraddr};" \ 403 "source ${scriptaddr}\0" \ 404 "installer=load mmc 0:2 $load_addr " \ 405 "/flex_installer_arm64.itb; " \ 406 "env exists mcinitcmd && run mcinitcmd && " \ 407 "mmc read 0x80001000 0x6800 0x800;" \ 408 "fsl_mc lazyapply dpl 0x80001000;" \ 409 "bootm $load_addr#ls1088ardb\0" \ 410 "qspi_bootcmd=echo Trying load from qspi..;" \ 411 "sf probe && sf read $load_addr " \ 412 "$kernel_addr $kernel_size ; env exists secureboot " \ 413 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 414 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 415 "bootm $load_addr#$BOARD\0" \ 416 "sd_bootcmd=echo Trying load from sd card..;" \ 417 "mmcinfo; mmc read $load_addr " \ 418 "$kernel_addr_sd $kernel_size_sd ;" \ 419 "env exists secureboot && mmc read $kernelheader_addr_r "\ 420 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 421 " && esbc_validate ${kernelheader_addr_r};" \ 422 "bootm $load_addr#$BOARD\0" 423 #else 424 #define CONFIG_EXTRA_ENV_SETTINGS \ 425 "BOARD=ls1088ardb\0" \ 426 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 427 "ramdisk_addr=0x800000\0" \ 428 "ramdisk_size=0x2000000\0" \ 429 "fdt_high=0xa0000000\0" \ 430 "initrd_high=0xffffffffffffffff\0" \ 431 "fdt_addr=0x64f00000\0" \ 432 "kernel_addr=0x1000000\0" \ 433 "kernel_addr_sd=0x8000\0" \ 434 "kernelhdr_addr_sd=0x4000\0" \ 435 "kernel_start=0x580100000\0" \ 436 "kernelheader_start=0x580800000\0" \ 437 "scriptaddr=0x80000000\0" \ 438 "scripthdraddr=0x80080000\0" \ 439 "fdtheader_addr_r=0x80100000\0" \ 440 "kernelheader_addr=0x800000\0" \ 441 "kernelheader_addr_r=0x80200000\0" \ 442 "kernel_addr_r=0x81000000\0" \ 443 "kernelheader_size=0x40000\0" \ 444 "fdt_addr_r=0x90000000\0" \ 445 "load_addr=0xa0000000\0" \ 446 "kernel_size=0x2800000\0" \ 447 "kernel_size_sd=0x14000\0" \ 448 "kernelhdr_size_sd=0x10\0" \ 449 MC_INIT_CMD \ 450 BOOTENV \ 451 "boot_scripts=ls1088ardb_boot.scr\0" \ 452 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 453 "scan_dev_for_boot_part=" \ 454 "part list ${devtype} ${devnum} devplist; " \ 455 "env exists devplist || setenv devplist 1; " \ 456 "for distro_bootpart in ${devplist}; do " \ 457 "if fstype ${devtype} " \ 458 "${devnum}:${distro_bootpart} " \ 459 "bootfstype; then " \ 460 "run scan_dev_for_boot; " \ 461 "fi; " \ 462 "done\0" \ 463 "boot_a_script=" \ 464 "load ${devtype} ${devnum}:${distro_bootpart} " \ 465 "${scriptaddr} ${prefix}${script}; " \ 466 "env exists secureboot && load ${devtype} " \ 467 "${devnum}:${distro_bootpart} " \ 468 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 469 "&& esbc_validate ${scripthdraddr};" \ 470 "source ${scriptaddr}\0" \ 471 "installer=load mmc 0:2 $load_addr " \ 472 "/flex_installer_arm64.itb; " \ 473 "env exists mcinitcmd && run mcinitcmd && " \ 474 "mmc read 0x80001000 0x6800 0x800;" \ 475 "fsl_mc lazyapply dpl 0x80001000;" \ 476 "bootm $load_addr#ls1088ardb\0" \ 477 "qspi_bootcmd=echo Trying load from qspi..;" \ 478 "sf probe && sf read $load_addr " \ 479 "$kernel_addr $kernel_size ; env exists secureboot " \ 480 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 481 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 482 "bootm $load_addr#$BOARD\0" \ 483 "sd_bootcmd=echo Trying load from sd card..;" \ 484 "mmcinfo; mmc read $load_addr " \ 485 "$kernel_addr_sd $kernel_size_sd ;" \ 486 "env exists secureboot && mmc read $kernelheader_addr_r "\ 487 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 488 " && esbc_validate ${kernelheader_addr_r};" \ 489 "bootm $load_addr#$BOARD\0" 490 #endif /* CONFIG_TFABOOT */ 491 492 #undef CONFIG_BOOTCOMMAND 493 #ifdef CONFIG_TFABOOT 494 #define QSPI_NOR_BOOTCOMMAND \ 495 "sf read 0x80001000 0xd00000 0x100000;" \ 496 "env exists mcinitcmd && env exists secureboot " \ 497 " && sf read 0x80780000 0x780000 0x100000 " \ 498 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 499 "&& fsl_mc lazyapply dpl 0x80001000;" \ 500 "run distro_bootcmd;run qspi_bootcmd;" \ 501 "env exists secureboot && esbc_halt;" 502 #define SD_BOOTCOMMAND \ 503 "env exists mcinitcmd && mmcinfo; " \ 504 "mmc read 0x80001000 0x6800 0x800; " \ 505 "env exists mcinitcmd && env exists secureboot " \ 506 " && mmc read 0x80780000 0x3C00 0x10 " \ 507 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 508 "&& fsl_mc lazyapply dpl 0x80001000;" \ 509 "run distro_bootcmd;run sd_bootcmd;" \ 510 "env exists secureboot && esbc_halt;" 511 #else 512 #if defined(CONFIG_QSPI_BOOT) 513 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 514 #define CONFIG_BOOTCOMMAND \ 515 "sf read 0x80001000 0xd00000 0x100000;" \ 516 "env exists mcinitcmd && env exists secureboot " \ 517 " && sf read 0x80780000 0x780000 0x100000 " \ 518 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 519 "&& fsl_mc lazyapply dpl 0x80001000;" \ 520 "run distro_bootcmd;run qspi_bootcmd;" \ 521 "env exists secureboot && esbc_halt;" 522 523 /* Try to boot an on-SD kernel first, then do normal distro boot */ 524 #elif defined(CONFIG_SD_BOOT) 525 #define CONFIG_BOOTCOMMAND \ 526 "env exists mcinitcmd && mmcinfo; " \ 527 "mmc read 0x80001000 0x6800 0x800; " \ 528 "env exists mcinitcmd && env exists secureboot " \ 529 " && mmc read 0x80780000 0x3C00 0x10 " \ 530 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 531 "&& fsl_mc lazyapply dpl 0x80001000;" \ 532 "run distro_bootcmd;run sd_bootcmd;" \ 533 "env exists secureboot && esbc_halt;" 534 #endif 535 #endif /* CONFIG_TFABOOT */ 536 537 /* MAC/PHY configuration */ 538 #ifdef CONFIG_FSL_MC_ENET 539 #define CONFIG_PHYLIB 540 541 #define CONFIG_PHY_VITESSE 542 #define AQ_PHY_ADDR1 0x00 543 #define AQR105_IRQ_MASK 0x00000004 544 545 #define QSGMII1_PORT1_PHY_ADDR 0x0c 546 #define QSGMII1_PORT2_PHY_ADDR 0x0d 547 #define QSGMII1_PORT3_PHY_ADDR 0x0e 548 #define QSGMII1_PORT4_PHY_ADDR 0x0f 549 #define QSGMII2_PORT1_PHY_ADDR 0x1c 550 #define QSGMII2_PORT2_PHY_ADDR 0x1d 551 #define QSGMII2_PORT3_PHY_ADDR 0x1e 552 #define QSGMII2_PORT4_PHY_ADDR 0x1f 553 554 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 555 #define CONFIG_PHY_GIGE 556 #endif 557 #endif 558 559 /* MMC */ 560 #ifdef CONFIG_MMC 561 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 562 #endif 563 564 #ifndef SPL_NO_ENV 565 566 #define BOOT_TARGET_DEVICES(func) \ 567 func(MMC, mmc, 0) \ 568 func(SCSI, scsi, 0) \ 569 func(DHCP, dhcp, na) 570 #include <config_distro_bootcmd.h> 571 #endif 572 573 #include <asm/fsl_secure_boot.h> 574 575 #endif /* __LS1088A_RDB_H */ 576