1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #define CONFIG_MISC_INIT_R 13 14 #if defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 16 #define CONFIG_ENV_SECT_SIZE 0x40000 17 #elif defined(CONFIG_SD_BOOT) 18 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 19 #define CONFIG_SYS_MMC_ENV_DEV 0 20 #define CONFIG_ENV_SIZE 0x2000 21 #else 22 #define CONFIG_ENV_IS_IN_FLASH 23 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 24 #define CONFIG_ENV_SECT_SIZE 0x20000 25 #define CONFIG_ENV_SIZE 0x20000 26 #endif 27 28 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 29 #ifndef CONFIG_SPL_BUILD 30 #define CONFIG_QIXIS_I2C_ACCESS 31 #endif 32 #define SYS_NO_FLASH 33 #undef CONFIG_CMD_IMLS 34 #endif 35 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_DDR_CLK_FREQ 100000000 38 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 39 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 40 41 #define CONFIG_DDR_SPD 42 #ifdef CONFIG_EMU 43 #define CONFIG_SYS_FSL_DDR_EMU 44 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 45 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 46 #else 47 #define CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 50 #endif 51 #define SPD_EEPROM_ADDRESS 0x51 52 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 53 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 54 55 56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 57 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 58 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 59 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 60 61 #define CONFIG_SYS_NOR0_CSPR \ 62 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 63 CSPR_PORT_SIZE_16 | \ 64 CSPR_MSEL_NOR | \ 65 CSPR_V) 66 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 72 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 73 FTIM0_NOR_TEADC(0x1) | \ 74 FTIM0_NOR_TEAHC(0x1)) 75 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 76 FTIM1_NOR_TRAD_NOR(0x1)) 77 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 78 FTIM2_NOR_TCH(0x0) | \ 79 FTIM2_NOR_TWP(0x1)) 80 #define CONFIG_SYS_NOR_FTIM3 0x04000000 81 #define CONFIG_SYS_IFC_CCR 0x01000000 82 83 #ifndef SYS_NO_FLASH 84 #define CONFIG_FLASH_CFI_DRIVER 85 #define CONFIG_SYS_FLASH_CFI 86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 87 #define CONFIG_SYS_FLASH_QUIET_TEST 88 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 89 90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 91 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 92 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 93 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 94 95 #define CONFIG_SYS_FLASH_EMPTY_INFO 96 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 97 #endif 98 #endif 99 100 #ifndef SPL_NO_IFC 101 #define CONFIG_NAND_FSL_IFC 102 #endif 103 104 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 105 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 106 107 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 108 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 109 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 110 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 111 | CSPR_V) 112 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 113 114 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 115 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 116 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 117 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 118 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 119 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 120 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 121 122 #define CONFIG_SYS_NAND_ONFI_DETECTION 123 124 /* ONFI NAND Flash mode0 Timing Params */ 125 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 126 FTIM0_NAND_TWP(0x18) | \ 127 FTIM0_NAND_TWCHT(0x07) | \ 128 FTIM0_NAND_TWH(0x0a)) 129 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 130 FTIM1_NAND_TWBE(0x39) | \ 131 FTIM1_NAND_TRR(0x0e) | \ 132 FTIM1_NAND_TRP(0x18)) 133 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 134 FTIM2_NAND_TREH(0x0a) | \ 135 FTIM2_NAND_TWHRE(0x1e)) 136 #define CONFIG_SYS_NAND_FTIM3 0x0 137 138 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 139 #define CONFIG_SYS_MAX_NAND_DEVICE 1 140 #define CONFIG_MTD_NAND_VERIFY_WRITE 141 #define CONFIG_CMD_NAND 142 143 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 144 145 #ifndef SPL_NO_QIXIS 146 #define CONFIG_FSL_QIXIS 147 #endif 148 149 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 150 #define QIXIS_BRDCFG4_OFFSET 0x54 151 #define QIXIS_LBMAP_SWITCH 2 152 #define QIXIS_QMAP_MASK 0xe0 153 #define QIXIS_QMAP_SHIFT 5 154 #define QIXIS_LBMAP_MASK 0x1f 155 #define QIXIS_LBMAP_SHIFT 5 156 #define QIXIS_LBMAP_DFLTBANK 0x00 157 #define QIXIS_LBMAP_ALTBANK 0x20 158 #define QIXIS_LBMAP_SD 0x00 159 #define QIXIS_LBMAP_EMMC 0x00 160 #define QIXIS_LBMAP_SD_QSPI 0x00 161 #define QIXIS_LBMAP_QSPI 0x00 162 #define QIXIS_RCW_SRC_SD 0x40 163 #define QIXIS_RCW_SRC_EMMC 0x41 164 #define QIXIS_RCW_SRC_QSPI 0x62 165 #define QIXIS_RST_CTL_RESET 0x31 166 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 167 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 168 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 169 #define QIXIS_RST_FORCE_MEM 0x01 170 171 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 172 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 173 | CSPR_PORT_SIZE_8 \ 174 | CSPR_MSEL_GPCM \ 175 | CSPR_V) 176 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_GPCM \ 179 | CSPR_V) 180 181 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 182 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 183 /* QIXIS Timing parameters*/ 184 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 185 FTIM0_GPCM_TEADC(0x0e) | \ 186 FTIM0_GPCM_TEAHC(0x0e)) 187 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 188 FTIM1_GPCM_TRAD(0x3f)) 189 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 190 FTIM2_GPCM_TCH(0xf) | \ 191 FTIM2_GPCM_TWP(0x3E)) 192 #define SYS_FPGA_CS_FTIM3 0x0 193 194 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 195 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 196 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 197 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 198 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 199 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 200 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 201 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 202 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 203 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 204 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 205 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 206 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 207 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 208 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 209 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 210 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 211 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 212 #else 213 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 214 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 215 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 216 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 217 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 218 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 219 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 220 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 221 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 222 #endif 223 224 225 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 226 227 #define I2C_MUX_CH_VOL_MONITOR 0xA 228 /* Voltage monitor on channel 2*/ 229 #define I2C_VOL_MONITOR_ADDR 0x63 230 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 231 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 232 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 233 #define I2C_SVDD_MONITOR_ADDR 0x4F 234 235 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" 236 #define CONFIG_VID 237 238 /* The lowest and highest voltage allowed for LS1088ARDB */ 239 #define VDD_MV_MIN 819 240 #define VDD_MV_MAX 1212 241 242 #define CONFIG_VOL_MONITOR_LTC3882_SET 243 #define CONFIG_VOL_MONITOR_LTC3882_READ 244 245 /* PM Bus commands code for LTC3882*/ 246 #define PMBUS_CMD_PAGE 0x0 247 #define PMBUS_CMD_READ_VOUT 0x8B 248 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 249 #define PMBUS_CMD_VOUT_COMMAND 0x21 250 251 #define PWM_CHANNEL0 0x0 252 253 /* 254 * I2C bus multiplexer 255 */ 256 #define I2C_MUX_PCA_ADDR_PRI 0x77 257 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 258 #define I2C_RETIMER_ADDR 0x18 259 #define I2C_MUX_CH_DEFAULT 0x8 260 #define I2C_MUX_CH5 0xD 261 262 #ifndef SPL_NO_RTC 263 /* 264 * RTC configuration 265 */ 266 #define RTC 267 #define CONFIG_RTC_PCF8563 1 268 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 269 #define CONFIG_CMD_DATE 270 #endif 271 272 /* EEPROM */ 273 #define CONFIG_ID_EEPROM 274 #define CONFIG_SYS_I2C_EEPROM_NXID 275 #define CONFIG_SYS_EEPROM_BUS_NUM 0 276 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 280 281 #ifndef SPL_NO_QSPI 282 /* QSPI device */ 283 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 284 #define CONFIG_FSL_QSPI 285 #define FSL_QSPI_FLASH_SIZE (1 << 26) 286 #define FSL_QSPI_FLASH_NUM 2 287 #endif 288 #endif 289 290 #define CONFIG_CMD_MEMINFO 291 #define CONFIG_SYS_MEMTEST_START 0x80000000 292 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 293 294 #ifdef CONFIG_SPL_BUILD 295 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 296 #else 297 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 298 #endif 299 300 #define CONFIG_FSL_MEMAC 301 302 #ifndef SPL_NO_ENV 303 /* Initial environment variables */ 304 #if defined(CONFIG_QSPI_BOOT) 305 #define MC_INIT_CMD \ 306 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 307 "sf read 0x80100000 0xE00000 0x100000;" \ 308 "env exists secureboot && " \ 309 "sf read 0x80700000 0x700000 0x40000 && " \ 310 "sf read 0x80740000 0x740000 0x40000 && " \ 311 "esbc_validate 0x80700000 && " \ 312 "esbc_validate 0x80740000 ;" \ 313 "fsl_mc start mc 0x80000000 0x80100000\0" \ 314 "mcmemsize=0x70000000\0" 315 #elif defined(CONFIG_SD_BOOT) 316 #define MC_INIT_CMD \ 317 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 318 "mmc read 0x80100000 0x7000 0x800;" \ 319 "env exists secureboot && " \ 320 "mmc read 0x80700000 0x3800 0x10 && " \ 321 "mmc read 0x80740000 0x3A00 0x10 && " \ 322 "esbc_validate 0x80700000 && " \ 323 "esbc_validate 0x80740000 ;" \ 324 "fsl_mc start mc 0x80000000 0x80100000\0" \ 325 "mcmemsize=0x70000000\0" 326 #endif 327 328 #undef CONFIG_EXTRA_ENV_SETTINGS 329 #define CONFIG_EXTRA_ENV_SETTINGS \ 330 "BOARD=ls1088ardb\0" \ 331 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 332 "ramdisk_addr=0x800000\0" \ 333 "ramdisk_size=0x2000000\0" \ 334 "fdt_high=0xa0000000\0" \ 335 "initrd_high=0xffffffffffffffff\0" \ 336 "fdt_addr=0x64f00000\0" \ 337 "kernel_addr=0x1000000\0" \ 338 "kernel_addr_sd=0x8000\0" \ 339 "kernelhdr_addr_sd=0x4000\0" \ 340 "kernel_start=0x580100000\0" \ 341 "kernelheader_start=0x580800000\0" \ 342 "scriptaddr=0x80000000\0" \ 343 "scripthdraddr=0x80080000\0" \ 344 "fdtheader_addr_r=0x80100000\0" \ 345 "kernelheader_addr=0x800000\0" \ 346 "kernelheader_addr_r=0x80200000\0" \ 347 "kernel_addr_r=0x81000000\0" \ 348 "kernelheader_size=0x40000\0" \ 349 "fdt_addr_r=0x90000000\0" \ 350 "load_addr=0xa0000000\0" \ 351 "kernel_size=0x2800000\0" \ 352 "kernel_size_sd=0x14000\0" \ 353 "kernelhdr_size_sd=0x10\0" \ 354 MC_INIT_CMD \ 355 BOOTENV \ 356 "boot_scripts=ls1088ardb_boot.scr\0" \ 357 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 358 "scan_dev_for_boot_part=" \ 359 "part list ${devtype} ${devnum} devplist; " \ 360 "env exists devplist || setenv devplist 1; " \ 361 "for distro_bootpart in ${devplist}; do " \ 362 "if fstype ${devtype} " \ 363 "${devnum}:${distro_bootpart} " \ 364 "bootfstype; then " \ 365 "run scan_dev_for_boot; " \ 366 "fi; " \ 367 "done\0" \ 368 "scan_dev_for_boot=" \ 369 "echo Scanning ${devtype} " \ 370 "${devnum}:${distro_bootpart}...; " \ 371 "for prefix in ${boot_prefixes}; do " \ 372 "run scan_dev_for_scripts; " \ 373 "done;\0" \ 374 "boot_a_script=" \ 375 "load ${devtype} ${devnum}:${distro_bootpart} " \ 376 "${scriptaddr} ${prefix}${script}; " \ 377 "env exists secureboot && load ${devtype} " \ 378 "${devnum}:${distro_bootpart} " \ 379 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 380 "&& esbc_validate ${scripthdraddr};" \ 381 "source ${scriptaddr}\0" \ 382 "installer=load mmc 0:2 $load_addr " \ 383 "/flex_installer_arm64.itb; " \ 384 "env exists mcinitcmd && run mcinitcmd && " \ 385 "mmc read 0x80200000 0x6800 0x800;" \ 386 "fsl_mc apply dpl 0x80200000;" \ 387 "bootm $load_addr#ls1088ardb\0" \ 388 "qspi_bootcmd=echo Trying load from qspi..;" \ 389 "sf probe && sf read $load_addr " \ 390 "$kernel_addr $kernel_size ; env exists secureboot " \ 391 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 392 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 393 "bootm $load_addr#$BOARD\0" \ 394 "sd_bootcmd=echo Trying load from sd card..;" \ 395 "mmcinfo; mmc read $load_addr " \ 396 "$kernel_addr_sd $kernel_size_sd ;" \ 397 "env exists secureboot && mmc read $kernelheader_addr_r "\ 398 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 399 " && esbc_validate ${kernelheader_addr_r};" \ 400 "bootm $load_addr#$BOARD\0" 401 402 #undef CONFIG_BOOTCOMMAND 403 #if defined(CONFIG_QSPI_BOOT) 404 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 405 #define CONFIG_BOOTCOMMAND \ 406 "sf read 0x80200000 0xd00000 0x100000;" \ 407 "env exists mcinitcmd && env exists secureboot " \ 408 " && sf read 0x80780000 0x780000 0x100000 " \ 409 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 410 "&& fsl_mc apply dpl 0x80200000;" \ 411 "run distro_bootcmd;run qspi_bootcmd;" \ 412 "env exists secureboot && esbc_halt;" 413 414 /* Try to boot an on-SD kernel first, then do normal distro boot */ 415 #elif defined(CONFIG_SD_BOOT) 416 #define CONFIG_BOOTCOMMAND \ 417 "env exists mcinitcmd && mmcinfo; " \ 418 "mmc read 0x80200000 0x6800 0x800; " \ 419 "env exists mcinitcmd && env exists secureboot " \ 420 " && mmc read 0x80780000 0x3800 0x10 " \ 421 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 422 "&& fsl_mc apply dpl 0x80200000;" \ 423 "run distro_bootcmd;run sd_bootcmd;" \ 424 "env exists secureboot && esbc_halt;" 425 #endif 426 427 /* MAC/PHY configuration */ 428 #ifdef CONFIG_FSL_MC_ENET 429 #define CONFIG_PHYLIB_10G 430 #define CONFIG_PHY_GIGE 431 #define CONFIG_PHYLIB 432 433 #define CONFIG_PHY_VITESSE 434 #define CONFIG_PHY_AQUANTIA 435 #define AQ_PHY_ADDR1 0x00 436 #define AQR105_IRQ_MASK 0x00000004 437 438 #define QSGMII1_PORT1_PHY_ADDR 0x0c 439 #define QSGMII1_PORT2_PHY_ADDR 0x0d 440 #define QSGMII1_PORT3_PHY_ADDR 0x0e 441 #define QSGMII1_PORT4_PHY_ADDR 0x0f 442 #define QSGMII2_PORT1_PHY_ADDR 0x1c 443 #define QSGMII2_PORT2_PHY_ADDR 0x1d 444 #define QSGMII2_PORT3_PHY_ADDR 0x1e 445 #define QSGMII2_PORT4_PHY_ADDR 0x1f 446 447 #define CONFIG_MII 448 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 449 #define CONFIG_PHY_GIGE 450 #endif 451 #endif 452 453 /* MMC */ 454 #ifdef CONFIG_MMC 455 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 456 #endif 457 458 #ifndef SPL_NO_ENV 459 460 #define BOOT_TARGET_DEVICES(func) \ 461 func(MMC, mmc, 0) \ 462 func(SCSI, scsi, 0) \ 463 func(DHCP, dhcp, na) 464 #include <config_distro_bootcmd.h> 465 #endif 466 467 #include <asm/fsl_secure_boot.h> 468 469 #endif /* __LS1088A_RDB_H */ 470