1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_RDB_H 8 #define __LS1088A_RDB_H 9 10 #include "ls1088a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO_LATE 13 14 #if defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_ENV_IS_IN_SPI_FLASH 16 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 17 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 18 #define CONFIG_ENV_SECT_SIZE 0x40000 19 #else 20 #define CONFIG_ENV_IS_IN_FLASH 21 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 22 #define CONFIG_ENV_SECT_SIZE 0x20000 23 #define CONFIG_ENV_SIZE 0x20000 24 #endif 25 26 #if defined(CONFIG_QSPI_BOOT) 27 #define CONFIG_QIXIS_I2C_ACCESS 28 #define SYS_NO_FLASH 29 #undef CONFIG_CMD_IMLS 30 #endif 31 32 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_DDR_CLK_FREQ 100000000 34 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 36 37 #define CONFIG_DDR_SPD 38 #ifdef CONFIG_EMU 39 #define CONFIG_SYS_FSL_DDR_EMU 40 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 41 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 42 #else 43 #define CONFIG_DDR_ECC 44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 45 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 46 #endif 47 #define SPD_EEPROM_ADDRESS 0x51 48 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 50 51 52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 53 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 54 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 55 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 56 57 #define CONFIG_SYS_NOR0_CSPR \ 58 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 59 CSPR_PORT_SIZE_16 | \ 60 CSPR_MSEL_NOR | \ 61 CSPR_V) 62 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 63 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 64 CSPR_PORT_SIZE_16 | \ 65 CSPR_MSEL_NOR | \ 66 CSPR_V) 67 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 68 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 69 FTIM0_NOR_TEADC(0x1) | \ 70 FTIM0_NOR_TEAHC(0x1)) 71 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 72 FTIM1_NOR_TRAD_NOR(0x1)) 73 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 74 FTIM2_NOR_TCH(0x0) | \ 75 FTIM2_NOR_TWP(0x1)) 76 #define CONFIG_SYS_NOR_FTIM3 0x04000000 77 #define CONFIG_SYS_IFC_CCR 0x01000000 78 79 #ifndef SYS_NO_FLASH 80 #define CONFIG_FLASH_CFI_DRIVER 81 #define CONFIG_SYS_FLASH_CFI 82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 83 #define CONFIG_SYS_FLASH_QUIET_TEST 84 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 85 86 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 87 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 88 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 89 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 90 91 #define CONFIG_SYS_FLASH_EMPTY_INFO 92 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 93 #endif 94 #endif 95 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 96 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 97 98 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 99 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 100 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 101 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 102 | CSPR_V) 103 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 104 105 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 106 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 107 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 108 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 109 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 110 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 111 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 112 113 #define CONFIG_SYS_NAND_ONFI_DETECTION 114 115 /* ONFI NAND Flash mode0 Timing Params */ 116 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 117 FTIM0_NAND_TWP(0x18) | \ 118 FTIM0_NAND_TWCHT(0x07) | \ 119 FTIM0_NAND_TWH(0x0a)) 120 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 121 FTIM1_NAND_TWBE(0x39) | \ 122 FTIM1_NAND_TRR(0x0e) | \ 123 FTIM1_NAND_TRP(0x18)) 124 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 125 FTIM2_NAND_TREH(0x0a) | \ 126 FTIM2_NAND_TWHRE(0x1e)) 127 #define CONFIG_SYS_NAND_FTIM3 0x0 128 129 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 131 #define CONFIG_MTD_NAND_VERIFY_WRITE 132 133 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 134 135 #define CONFIG_FSL_QIXIS 136 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 137 #define QIXIS_LBMAP_SWITCH 2 138 #define QIXIS_QMAP_MASK 0xe0 139 #define QIXIS_QMAP_SHIFT 5 140 #define QIXIS_LBMAP_MASK 0x1f 141 #define QIXIS_LBMAP_SHIFT 5 142 #define QIXIS_LBMAP_DFLTBANK 0x00 143 #define QIXIS_LBMAP_ALTBANK 0x20 144 #define QIXIS_LBMAP_SD 0x00 145 #define QIXIS_LBMAP_SD_QSPI 0x00 146 #define QIXIS_LBMAP_QSPI 0x00 147 #define QIXIS_RCW_SRC_SD 0x40 148 #define QIXIS_RCW_SRC_QSPI 0x62 149 #define QIXIS_RST_CTL_RESET 0x31 150 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 151 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 152 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 153 #define QIXIS_RST_FORCE_MEM 0x01 154 155 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 156 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 157 | CSPR_PORT_SIZE_8 \ 158 | CSPR_MSEL_GPCM \ 159 | CSPR_V) 160 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 161 | CSPR_PORT_SIZE_8 \ 162 | CSPR_MSEL_GPCM \ 163 | CSPR_V) 164 165 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 166 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 167 /* QIXIS Timing parameters*/ 168 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 169 FTIM0_GPCM_TEADC(0x0e) | \ 170 FTIM0_GPCM_TEAHC(0x0e)) 171 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 172 FTIM1_GPCM_TRAD(0x3f)) 173 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 174 FTIM2_GPCM_TCH(0xf) | \ 175 FTIM2_GPCM_TWP(0x3E)) 176 #define SYS_FPGA_CS_FTIM3 0x0 177 178 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 179 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 180 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 181 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 182 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 183 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 184 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 185 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 186 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 187 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 188 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 189 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 190 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 191 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 192 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 193 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 194 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 195 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 196 #else 197 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 198 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 199 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 200 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 201 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 202 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 203 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 204 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 205 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 206 #endif 207 208 209 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 210 211 /* 212 * I2C bus multiplexer 213 */ 214 #define I2C_MUX_PCA_ADDR_PRI 0x77 215 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 216 #define I2C_RETIMER_ADDR 0x18 217 #define I2C_MUX_CH_DEFAULT 0x8 218 #define I2C_MUX_CH5 0xD 219 /* 220 * RTC configuration 221 */ 222 #define RTC 223 #define CONFIG_RTC_PCF8563 1 224 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 225 #define CONFIG_CMD_DATE 226 227 /* EEPROM */ 228 #define CONFIG_ID_EEPROM 229 #define CONFIG_SYS_I2C_EEPROM_NXID 230 #define CONFIG_SYS_EEPROM_BUS_NUM 0 231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 235 236 /* QSPI device */ 237 #if defined(CONFIG_QSPI_BOOT) 238 #define CONFIG_FSL_QSPI 239 #define CONFIG_SPI_FLASH_SPANSION 240 #define FSL_QSPI_FLASH_SIZE (1 << 26) 241 #define FSL_QSPI_FLASH_NUM 2 242 #endif 243 244 #define CONFIG_CMD_MEMINFO 245 #define CONFIG_CMD_MEMTEST 246 #define CONFIG_SYS_MEMTEST_START 0x80000000 247 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 248 249 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 250 251 #define CONFIG_FSL_MEMAC 252 253 /* Initial environment variables */ 254 #if defined(CONFIG_QSPI_BOOT) 255 #undef CONFIG_EXTRA_ENV_SETTINGS 256 #define CONFIG_EXTRA_ENV_SETTINGS \ 257 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 258 "loadaddr=0x90100000\0" \ 259 "kernel_addr=0x100000\0" \ 260 "ramdisk_addr=0x800000\0" \ 261 "ramdisk_size=0x2000000\0" \ 262 "fdt_high=0xa0000000\0" \ 263 "initrd_high=0xffffffffffffffff\0" \ 264 "kernel_start=0x1000000\0" \ 265 "kernel_load=0xa0000000\0" \ 266 "kernel_size=0x2800000\0" \ 267 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 268 "sf read 0x80100000 0xE00000 0x100000;" \ 269 "fsl_mc start mc 0x80000000 0x80100000\0" \ 270 "mcmemsize=0x70000000 \0" 271 272 #endif 273 274 /* MAC/PHY configuration */ 275 #ifdef CONFIG_FSL_MC_ENET 276 #define CONFIG_PHYLIB_10G 277 #define CONFIG_PHY_GIGE 278 #define CONFIG_PHYLIB 279 280 #define CONFIG_PHY_VITESSE 281 #define CONFIG_PHY_AQUANTIA 282 #define AQ_PHY_ADDR1 0x00 283 #define AQR105_IRQ_MASK 0x00000004 284 285 #define QSGMII1_PORT1_PHY_ADDR 0x0c 286 #define QSGMII1_PORT2_PHY_ADDR 0x0d 287 #define QSGMII1_PORT3_PHY_ADDR 0x0e 288 #define QSGMII1_PORT4_PHY_ADDR 0x0f 289 #define QSGMII2_PORT1_PHY_ADDR 0x1c 290 #define QSGMII2_PORT2_PHY_ADDR 0x1d 291 #define QSGMII2_PORT3_PHY_ADDR 0x1e 292 #define QSGMII2_PORT4_PHY_ADDR 0x1f 293 294 #define CONFIG_MII 295 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 296 #define CONFIG_PHY_GIGE 297 #endif 298 299 /* MMC */ 300 #ifdef CONFIG_MMC 301 #define CONFIG_FSL_ESDHC 302 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 303 #endif 304 305 #undef CONFIG_CMDLINE_EDITING 306 #include <config_distro_defaults.h> 307 308 #define BOOT_TARGET_DEVICES(func) \ 309 func(USB, usb, 0) \ 310 func(MMC, mmc, 0) \ 311 func(SCSI, scsi, 0) \ 312 func(DHCP, dhcp, na) 313 #include <config_distro_bootcmd.h> 314 315 #include <asm/fsl_secure_boot.h> 316 317 #endif /* __LS1088A_RDB_H */ 318